DIGITAL PHASE LOCKED LOOP DESIGN

Abstract

Phase Locked Loops (PLLs) have been widely used in radio, telecommunications, computers other electronic applications. They may generate stable frequencies, recover a signal from a noisy communication channel, or distribute clock timing pulses in digital logic designs such as micro processors and can generate high frequency clocks using frequency multipliers. In this thesis, we present the design of Digital Phase Locked Loop (DPLL), which has low-power consumption and fast locking considerations. The previously proposed circuits for various units of PLL were modified for better performance and characteristics. Here we first systematically analyzed the working of basic PLL and its inner blocks from aspects of theoretical analysis and circuit operation. Based on the circuit architecture, both classifications and comparisons are made. Then we propose a high speed phase frequency detector. The proposed phase frequency detector is simple in its structure and has no glitch output as well as better phase characteristics. The speed of the proposed phase frequency detector is up to 16 GHz. Charge pump current is aimed at 150 μA and the output-frequency range of the oscillator is from 3.7GHz to 6.8GHz for 425-625mV control voltage range. The simulated PLL will use 100 MHz reference frequency. The lock time of proposed PLL is less than 0.45μs and average power consumption is 3.2 mw. V