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dc.contributor.authorMadan, Garima-
dc.guideDas Gupta, S.-
dc.guideNath, R.-
dc.guideTandon, V. K.-
dc.description.abstractThe increasing prominence of portable systems and the need to limit power consumption (and hence, heat dissipation) in very-high density ULSI chips have led to rapid and innovative developments in low-power design during the recent years. The driving forces behind these developments are portable applications requiring low power dissipation and high throughput, such as notebook computers, portable communication devices and personal digital assistants (PDAs). In most of these cases, the requirements of low power consumption must be met along with equally demanding goals of high chip density and high throughput. Hence, low-power design of digital integrated circuits has emerged as a very active and rapidly developing field of CMOS design. The methodologies, which are used to achieve low power consumption in digital systems span a wide range, from device/process level to algorithm level. Device characteristics (e.g., threshold voltage), device geometries and interconnect properties are significant factors in lowering the power consumption. Circuit-level measures such as the proper choice of circuit design styles, reduction of the voltage swing and clocking strategies can be used to reduce power dissipation at the transistor level. Architecture-level measures include smart power management of various system blocks, utilization of pipelining and parallelism, and design of bus structures. Finally, the power consumed by the system can be reduced by a proper selection of the data processing algorithms, specifically to minimize the number of switching events for a given task. In this thesis we considered the circuit level technique for low energy computation using the principle of adiabatic switching. Energy recovery using adiabatic switching is a relatively new idea. As part of low power circuit design, this thesis aims to reduce power consumption of digital circuits. Digital circuits are basic building blocks for the design of adiabatic or energy recovery systems. Hence we have designed most of digital circuits starting from logic gates (AND, OR, NAND, NOR, XOR, XNOR, INVERTER, BUFFER), latches, flip flops (D-FF), combinational circuits (adders, multiplexers) and sequential circuits (parallel-in-parallel-out shift registers) using 2N- [31 2N2P, ECRL and PFAL adiabatic logic families at 180 rim technology. Power consumption of PFAL adiabatic logic family is least in comparative to 2N-2N2P and ECRL adiabatic logic families. Maximum power consumption is obtained in ECRL family i.e. approximately 2.5 times greater than power consumption of 2N-2N2P logic family and 3.5 times greater than power consumption of PFAL logic family at various frequencies ranging from 350MHz to 500MHz.en_US
dc.typeM.Tech Dessertationen_US
Appears in Collections:MASTERS' THESES (Physics)

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