LOW POWER FPGA DESIGN: ARCHITECTURE, MODELING AND PERFORMANCE ISSUES

Abstract

This dissertation work investigates the effect of velocity saturation index and circuit activity in the context of joint optimization of supply and threshold voltage to meet power-performance constraints simultaneously. Extensive simulations are performed to study these effects in FPGA framework. An inverter level FPGA logic block model has been presented to incorporate deep sub-micron range delay behavior of MOSFET. Results show significant importance of velocity saturation index and activity factor in determining location of optimal supply and threshold voltage.