EFFFICIENT NANOSCALE VLSI STANDARD CELL LIBRARY CHARACTERIZATION USING A NOVEL DELAY MODEL

Abstract

Accurate estimation of delays in Static Timing Analysis (STA) using Non Linear Delay Model (NLDM) based Look Up Table (LUT) is a major challenge in nanome-ter range VLSI circuits. There are serious issues with NLDM based LUT due to the present method of arbitrary choice of input signal transition time trip and load capacitance. (C1) and resulting large number of HSPICE simulations with ad-hoc method adopted for achieving tolerable accuracy. In this dissertation, we present a systematic method to reduce standard cell library characterization time significantly achieving accuracy in a more systematic way. For this purpose we propose and use a simple and physics based logic gate delay model in which delay varies linearly with Ci and t,i,,, where Cl is the load capacitance and tri, is the input signal transition time of a standard cell. We also determine its region of validity in the (Cl, t,i,,) space. We express the delay model coefficients and model's region of validity as a function of inverter (or logic gate) size. We validate our model for all basic gates such as inverter and NAND using HSPICE: We extend our work to multi-stage standard cells too. We do not use device current/capacitance models in our work and hence the method is general enough to be valid with scaling. With the help of this new model, we were able 'to save approximately of 60% SPICE simulations during the standard cell library characterization. We observe that the delay obtained using our LUTs is as accurate as that of the delay obtained through traditional LUTs with the said saving in simulation time