NANOSCALE DG FINFETS: SCALING ISSUES, DEVICE OPTIMIZATION AND APPLICATION TO SRAMS

Abstract

Double gate FinFETs have emerged as promising devices that can replace bulk MOSFETs as we approach sub-45 nm technologies. In these devices the short channel effects are reduced because of better gate control and the use of a thin and lightly doped channel. In this dissertation report, a detailed analysis of the various scaling issues pertaining to DG FinFETs has been carried out through 2D simulations, including quantum corrections, using a state of the art device simulator. The effects of scaling down the device dimensions like gate length, fm thickness, gate oxide thickness and gate thickness were studied. The impacts on the transistor on current, off state leakage current, threshold voltage, transconductance, DIBL, subthreshold slope, and the gate leakage have been analyzed. The effect of variation of doping densities in the fm region was also studied. An attempt was made to optimize the DG FinFET devices to approach the ITRS targets for the year 2015 for HP (High Performance) applications. Source/Drain doping engineering, gate dielectric engineering, spacer engineering and metal gate work function engineering were explored for achieving optimal characteristics. Finally, a 6T SRAM cell was designed and simulated using the optimized FinFETs at 15 nm, using mixed mode simulations. The effects of work function modulation and Vdd scaling were examined using the read stability and write ability metrics based on conventional butterfly curves and N-curves. It was demonstrated that work function engineering can be an alternative method to improve the cell performance, without resorting to transistor sizing.