HIGH PERFORMANCE ADVANCE ENCRYPTION STANDARD IMPLEMENTATION ON FPGA

Abstract

In today's world most of the communication is done using electronic media. Data Security plays a vital role in such communication. In October 2000, the National Institute of Standards and Technology (NIST) selected the Rijndael as the Advanced Encryption Standard (AES) algorithm to replace the old Data Encryption Standard (DES).Till then four modes has been proposed by NIST. A fourth and recent mode of operation of AES proposed by NIST in November 2006, SP800-38D, Galois/Counter Mode of Operation (GCM), that provide not only data security through encryption but also massage authentication. Before GCM, SP800-38A only provided confidentiality and SP800-38B provided authentication. SP800-38C provided confidentiality using the counter mode and authentication. However the authentication technique in SP800-38C was not parallelizable and slowed down the throughput of the cipher. Hence, none of these three recommendations were suitable for high speed network and computer system applications. This work includes, demonstration and analysis of FPGA architectures for, SP800-38A (AES-ECB) and SP800-38D (AES-GCM) modes of AES algorithm with the view of enhancing their performance. AES-GCM is a complex unit, AES-ECB (Electronic Code-Book) is used as one of its internal component; so this thesis first presents efficient iterative and fully pipelined based hardware architectures for AES-ECB mode and then finally presents fully pipelined and parallelized hardware architecture for AES-GCM. Area optimization in above stated designs has been approached through implementing Sboxes of AES by Composite Field Arithmetic (CFA) technique and their comparison is made with respective LUTs (Look-Up tables) based designs. Since modular multiplier is a very important unit of AES-GCM, which not only very crucial to determine speed of design but also covers 50% of overall area of the design, there are two multipliers has been analyzed and used in final AES-GCM design. In this thesis, all the designs are implemented on multi-core Xilinx's virtex-4 FPGA platform.