DESIGN AND SIMULATION OF 32 BIT ALU BASED ON FEEDBACK SWITCH LOGIC

Abstract

This thesis presents the employment of Feedback Switch Logic (FSL) in the development of a 32-bit ALU unit. For the design of ALU, we have chosen Feedback Switch Logic (FSL) because it offers reduced capacitance, fast switching and input-switching dependent activity factor without the need of clock connection. The Arithmetic Logic Unit is a digital circuit that performs an arithmetic operation (addition, subtraction, etc.) and logic operations (Exclusive-OR, AND, etc.) between two numbers. Demand for performance at low power consumption in today's general purpose processor has put severe limitations on ALU design. ALU are also one of the most power consumed blocks in the processor and are often the possible location of hot-spots. Hence this thesis aims to reduce power consumption and improve performance using FSL. Three types of adders, two types of shifter structures and one logical unit have been designed in FSL and static CMOS logic styles. Comparisons are drawn among the various designed units and the best one in terms of high speed and low power is chosen. Finally we have done the proper organization of adders, shifter and logic unit to make complete ALU. Simulations have been performed in CADENCE Virtuoso Front to Back Design Environment on 90nm technology node. Simulation results show that 14% increase in speed has been achieved with FSL trading-off with an 8% increase in power consumption when compared to static CMOS logic.