DESIGN OF LOW POWER DIGITAL CIRCUITS AND REGISTER FILE USING ADIABATIC COMPLEMENTARY PASS-TRANSISTOR LOGIC

Abstract

Power dissipation has become a critical design issue in high performance applications, especially in portable and battery operated ASIC systems. With technology scaling, the impact of power dissipation is expected to gain significance. In order to optimize - the power consumption research at various levels of design, abstraction has been started and achieves ultra low power with optimum performance. In this thesis, we considered circuit level techniques for low energy computation using the principles of adiabatic switching. Energy- recovery using adiabatic switching is a relatively new idea. Although the concept of reversible logic and zero energy computing can be traced back to the early 1970's, the attempt to realize the concept in electronic circuits is a new endeavor. As a part of low power circuit design, this thesis aims to reduce power consumption of digital circuits and a typical processor component register file. Digital circuits are basic building blocks for the design of adiabatic or energy recovery systems. Hence, we have designed all the digital circuits starting from logic gates (AND, OR, NAND, NOR, XOR, XNOR, INVERTER, BUFFER), flip flops (D-FF, JK-FF), combinational circuits (adders, multiplexers, 4-bit ripple carry adder), and sequential circuits (4-bit shift register, 4-bit binary counter) using adiabatic complementary pass transistor logic (ACPL), PAL-2N which is one of the adiabatic logics and static CMOS logic at 90nm technology. The power consumption of digital circuits using ACPL is 75-92% lesser than static CMOS and 10-20% than PAL-2N at various frequencies ranging from 50MHz-300MHz. iii