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|Title:||SINGLE EVENT UPSET TOLERANT D-FLIP FLOP DESIGN IN 90nm PDSOI TECHNOLOGY|
|Authors:||Puvvala, Eswara Kumar|
|Keywords:||ELECTRONICS AND COMPUTER ENGINEERING;SINGLE EVENT;UPSET TOLERANT;PDSOI TECHNOLOGY|
|Abstract:||the scaled circuits to transient data upsets or soft errors has emerged as a major reliability concern. Soft error protection is very important for, enterprise computing and communication applications. Several designs today implement extensive error checking and correction (ECC) mainly for on chip memory. However, memory protection is not enough, because soft errors in flip flops and combinational logic are also significant contributors to the system-level SER (Soft Error Rate). For many designs, not only the memory elements but also latches and flip-flops, must be protected from soft errors. In this dissertation, a circuit level soft error mitigation technique for D-type flip flop has been proposed. The proposed design reduces the effect of single event upset during static data storage phase. The proposed design can be fabricated in the mainstream commercial CMOS process. The simulation results indicate that the proposed design has less area, power and delay overheads than the flip flop designs used in Triple Module Redundancy (TMR), Built in Soft Error Resilience (BISER) and Sense Amplifier Based flip flop. Case study for Combinational Logic Block (CLB) also proves that adaptation of proposed design in radiation hardened FPGA will significantly reduce the overall gate count when compared with the other radiation hardened flip flop designs. Simulations are carried out in SYNOPSIS HSPICE at 90nm PDSOI technology node. BSIMSOI model file is used for the simulation purpose. All waveforms are obtained from SYNOPSIS COSMOS SCOPE.|
|Research Supervisor/ Guide:||Dasgupta, S.|
|Appears in Collections:||MASTERS' THESES (E & C)|
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