A COMPARATIVE STUDY OF 61, 8T AND 9T DECANANO SRAM CELL

Abstract

Data retention and leakage current reduction are among the major area of concern in today's CMOS technology. Due to their higher speed SRAM based cache memories are commonly used. SRAM is also an important part of any system on chip design. Due to device scaling there are several design challenges for robust and low leakage SRAM design. SRAM cells are more susceptible to failure during read operation. In order to eliminate this problem new SRAM cells with higher read noise margin have been introduced. In this paper a comparative study of 6T, 8T and 9T SRAM cell has been carried out on the basis of read noise margin (RNM), write noise margin (WNM), read delay, write delay, data retention voltage (DR V), layout and average write power. Corner and statistical simulation of the noise margin has been carried out to analyze the effect of intrinsic parameter fluctuation. Both 8T SRAM cell and 9T SRAM cell provides higher read noise margin (around 4 times increase in RNM) as compared to 6T SRAM cell. Although the size of 9T SRAM cell is around 1.35 times higher than that of the 8T SRAM cell but it provides higher write stability. Due to single ended bit line sensing the write stability of 8T SRAM cell is greatly affected. The 8T SRAM cell provides a write "1" noise margin which is approximately 3 times smaller than that of the 9T SRAM cell. All the simulation has been carried out on 90nm CMOS technology.