FPGA IMPLEMENTATION OF GSM BASEBAND PROCESSING FOR RECONFIGURABLE SOFTWARE DEFINED RADIO

Abstract

Software defined radio is a feasible solution for reconfigurable radios, which can perform different functions at different times on the same hardware. The partial reconfiguration is the key feature of software defined radio. Partial reconfiguration is the ability of certain Field Programmable Gate Arrays (FPGAs) to reconfigure only selected portions of their programmable hardware while other portions continue to operate undisturbed. A FPGA can be partially reconfigured using a partial bitstream. We can use such a partial bitstream to change the structure of one part of an FPGA design as the rest of the device continues to operate and this reduces the reconfiguration time. The aim of this thesis is to design and , implement a software defined radio based wireless communication system (GSM). The baseband section of a wireless communication system is first simulated and then implemented in hardware. The performance of the baseband transmitter is analyzed using constellation and eye diagrams different signal-to noise ratio and different BT(bandwidth, time product) values, while considering an additive white Gaussian noise channel. The performance of the receiver is analyzed by comparing the bit error rates. The performance of the system in real time is also analyzed by implementing the system in hardware using Xilinx Virtex-4 field programmable gate array. A comparison of the simulation results with the results obtained from implementing the system on virtex-4 hardware is presented and discussed. The two different GSM baseband processing versions have been developed i.e., one is area optimized and the other is speed optimized. The total hardware resources occupied by these units have been reduced through time-sharing between modules.