Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/11931
Title: HARDWARE EFFICIENT DESIGN OF PARALLEL FIR FILTERS AND ITS APPLICATION TO 2D DWT
Authors: Kellampalli, Suresh
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;FIR FILTERS;2D DWT;|HARDWARE EFFICIENT DESIGN
Issue Date: 2008
Abstract: ABSTRACT Finite impulse response (FIR) filter is regarded as one of the major operations in digital signal processing. Parallel processing is a powerful technique because it can be used to increase the throughput of a FIR filter or reduce the power consumption of a FIR filter. Parallel FIR filters (i.e., realizing FIR filters in parallel) has got its various applications in 2D Discrete wavelet Transform (DWT), Motion Estimation in Video Compression, Equalizers and 2D FIR filters. However, a traditional parallel FIR filter implementation causes a linear increase in the hardware cost (area) by a factor of L, the block size i.e., level of parallelism. In many design situations, this large hardware penalty cannot be tolerated. Therefore, it is advantageous to produce parallel FIR filter implementations that require less area than traditional parallel FIR filtering structures. An approach to increase the throughput of FIR filters, with reduced complexity hardware based on fast FIR algorithms and fast short length linear convolution algorithms, were presented. Although their basic idea is the same, i.e., first derive smaller length fast parallel filters and then cascade or iterate these short-length filters for long block sizes, their starting point is not the same. These methods will have a simple and efficient control in the increase of hardware cost. These hardware efficient parallel FIR filters can be used for the fast implementation of 2D Discrete Wavelet Transform (DWT) than the other convolution and lifting based architectures. The focus of this thesis is to present the recent methods to realize the hardware efficient parallel FIR filters (i.e., by Fast FIR algorithms and Fast short convolution algorithms) and its application to 2D Discrete Wavelet Transform. The hardware simulation of these efficient structures are carried out in Modelsim and synthesized using Xilinx. A Matlab code is developed for finding the computational complexity of each method. The comparisons of these methods are also done. For 2D DWT the comparisons are done with the recent convolution based architectures. iii
URI: http://hdl.handle.net/123456789/11931
Other Identifiers: M.Tech
Research Supervisor/ Guide: Dasgupta, S.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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