Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/11926
Title: DESIGN OF SWITCHED CAPACITOR BASED LOW PASS SIGMA DELTA MODULATOR
Authors: Patluri, Bindu
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;CAPACITOR;DELTA MODULATOR;DESIGN OF SWITCHED
Issue Date: 2008
Abstract: The need to develop cost effective high resolution converters which can be integrated on the same chip along with the digital circuits led to the use of sigma-delta modulator (16,1\4). For the on-chip integration of these modulators design of EAM at low supply voltages becomes necessary. In audio and biomedical applications, low pass EOM is used. For implementing these modulators, Switched Capacitor (SC) technique is widely used due to its compatibility with the standard CMOS technology its ability to realize accurate signal processing function. The design of these modulators at low supply voltages of 1 V is challenging in terms of analog circuit performance. The design of low pass second order /AM at low supply voltage of 1 V has been presented in this dissertation. Behavioral modeling of the SC EOM using SD toolbox was done and simulated in Matlab and Simulink environment optimise SNR at architecture level and also to obtain the required circuit level specifications for achieving > 10 bits resolution. The nonidealities where reduced by proper selection and designing of circuit topologies. Two stage opamp has been used to account for reduction of magnitude and phase error of the integrator transfer function due to finite gain. Integrator has been designed to minimize distortion and charge injection. Dynamic latched comparator has been employed for power reduction. This modulator employs Auto-Zeroed Integrator for operation at high frequencies by eliminating the critical switches. This can be used to digitize electrical biomedical signals like Electro-cardiogram (ECG), Electroencephalogram (EEG), and Electroretinogram (ERG). The simulated results of the proposed /AM in standard CMOS 0.18 gm technology, using Tanner tools gave about 10 bits resolution for input at 4 kHz and clock frequency of 1 MHz with 1 V power supply.
URI: http://hdl.handle.net/123456789/11926
Other Identifiers: M.Tech
Research Supervisor/ Guide: Saxena, A. K.
Dasgupta, S.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

Files in This Item:
File Description SizeFormat 
ECDG14333.pdf3.36 MBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.