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|Title:||IMPLEMENTATION OF FLOATING POINT AND LOGARITHMIC NUMBER SYSTEM ARITHMETIC UNITS AND THEIR COMPARISON FOR FPGA|
|Keywords:||ELECTRONICS AND COMPUTER ENGINEERING|
|Abstract:||Floating point (FP) representation is commonly used to represent real numbers. Some papers have suggested the use of logarithmic number system (LNS) in addition to floating point. In LNS, a real number is represented as a fixed point logarithm. Therefore, multiplication and division in LNS are much simpler in comparison to that in FP, so the LNS can be beneficial if addition and subtraction can be performed with speed and accuracy equivalent to FP. LNS addition and subtraction requires interpolation technique for which some vales are stored in read only memory (ROM). In this dissertation, different sizes of ROMs are used for addition and subtraction, and their performances are compared to themselves and also to the floating point. To obtain good accuracy in LNS addition and subtraction, more values should be stored in the ROM. As a result, FPGA utilization increases. FP addition and subtraction are simple and does not require ROM. The problem is more aggravate in subtraction because the value of Iog2 x varies from -1 to -co as x varies from 0.5 to 0. So, more values are stored in ROM for x variation between 0.5 and 0. These values of x do not occur during addition. This is the reason that in LNS subtraction while increasing the ROM size, the values are added for the variation of x from 0.5 to 0 and keeping rest of the ROM same. One more problem with LNS addition and subtraction is that same ROM can not be used for both the operations. In this dissertation, LNS addition and subtraction are also performed using the fixed size ROM (46 values) without using interpolation and the advantage of this method is that same ROM can be used for both LNS addition and subtraction.|
|Appears in Collections:||MASTERS' DISSERTATIONS (E & C)|
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