Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/11909
Title: DESIGN AND SIMULATION OF CMOS BASED DELAY LOCKED LOOP FOR MULTIPHASE CLOCK GENERATION AND ITS APPLICATION AS A PROGRAMMABLE CLOCK MULTIPLIER
Authors: Gupta, Abhay
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;SIMULATION OF CMOS;MULTIPHASE CLOCK GENERATION;PROGRAMMABLE CLOCK MULTIPLIER
Issue Date: 2008
Abstract: Delay Locked Loops (DLLs) have been widely used in various applications like clock distribution networks (to remove clock skew), frequency multipliers (to generate high frequency clock) etc , where conventionally Phase Locked Loops (PLLs) were used. This is because DLLs offer several advantages over PLLs, in terms or their simplicity, stability, easy to design and integrate on chip, low power consumption and better jitter performance. In nowadays, more and more applications such as local oscillators in communication systems, on chip clock generators in high speed microprocessors and clock distribution networks in synchronous circuits employ DLL. So, the DLL will be more significant in future. In this thesis, in the first part the design of Delay Locked Loop for multiphase clock generation is presented at 180 nm technology node with low power and fast locking, considerations. The previously proposed circuits for various units of DLL were modified for better performance and characteristics at desired technology node. The operating frequency range of the proposed DLL is 170 MHz- 252 MHz. The simulations were carried in T-SPICE with 1.8 V power supply and 200 MHz reference frequency. The lock time of proposed DLL is less than 300 ns and average power consumption is 6.46 mw. In the later part of the thesis, the work is extended and the multiphase clocks obtained from the DLL, designed, are utilized for the purpose of frequency multiplication of the reference clock signal. A DLL based programmable frequency/clock multiplier with multiplication factor of '1X, 2X and 4X is proposed. The output frequencies. of DLL based frequency multiplier are 170 MHz — 252 MHz (multiply by 1), 340 MHz — 504 MHz (multiply by 2) and 680 MHz — 1.004 GHz (multiply by 4). We used the same reference frequency of 200 MHz and showed (through T-SPICE simulations) the output with 200 MHz, 400 MHz and 800 MHz, with exactly 50 % duty cycle, for multiplication factor of 1X, 2X and 4X respectively. The average power consumption in all the three cases is less than 10 mw.
URI: http://hdl.handle.net/123456789/11909
Other Identifiers: M.Tech
Research Supervisor/ Guide: Saxena, A. K.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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