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|Title:||FPGA BASED "PARALLEL IMPLEMENTATION OF DWT FOR IMAGE COMPRESSION|
|Authors:||Kumar, K. Prashanth|
|Keywords:||ELECTRONICS AND COMPUTER ENGINEERING|
|Abstract:||orthogonal Cohen-Daubechies-Feuvear (CDF) (2,2) wavelet with line-based method is proposed for FPGA implementation using lifting scheme. The FPGA based hardware implementation profits especially from the high parallelism in the architecture and the moderate number precision required to preserve the qualitative effects of the mathematical models. The proposed architecture is designed to generate 4 sub bands coefficients concurrently per clock cycle that can perform a 1-level decomposition of a N x N image in exactly N2 / 4 working clock cycles, without any line buffers at the column processor, thus reducing the time for line buffering but with an extra row processor and with 100% hardware utilization. Proposed architecture is first tested using MATLAB software, then VHDL code is written in Xilinx ISE 9.1 and simulated results are verified using Modelsim software. After fmal implementation .bit file is generated, which is burned on FPGA successfully|
|Appears in Collections:||MASTERS' DISSERTATIONS (E & C)|
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