DESIGN OF DIGITAL CIRCUITS USING DTGAL, CPAL AND ACPL FOR LOW POWER APPLICATIONS

Abstract

The never ending need for low power digital circuits has intrigued designers to explore new options in the world of circuit design. One approach that seems to be very promising is the energy-recovering (adiabatic) logic. Adiabatic circuits obtain low power consumption by restricting the current to flow across devices with low voltage drop and by recycling the energy stored on their capacitors. All the digital circuits both combinational and sequential can be designed using adiabatic logic. Adiabatic BCD code up-counter having lower power consumption than CMOS BCD code up-counter was designed using DTGAL at 180nm using SPICE. Digital circuits such as SRAM's are used extensively in modern processors as on-chip memories due to their large storage density. These memories consume large amount of power because of the large capacitance on bit lines word lines etc, and are frequently accessed. An adiabatic SRAM circuit consuming very lower power is designed using DTGAL, CPAL and ACPL at 180nm and 90nm using SPICE. The power consumption of three SRAM circuits was observed for different frequencies up to 500MHz. The SPICE simulation results show that ACPL is efficient technique both in terms of power consumption and area needed for the design.90nm ACPL SRAM has power consumption of 51% and 14% lesser than DTGAL and CPAL SRAM's respectively at 500MHz, also ACPL needed 39% and 18% lesser area than DTGAL and CPAL for SRAM circuit.