CPAL BASED DESIGN OF ARITHMETIC AND LOGIC CIRCUITS

Abstract

As the density and operating speed of CMOS chips increase, power dissipation has become a critical concern in the design of VLSI circuits, especially in mobile and portable electronic systems. In conventional CMOS circuits popular approaches to low power design include the reduction of supply voltage, node capacitance and switching activity. Adiabatic logic is a promising alternative low power design technique which is compatible with the energy savings that can be achieved through reductions in supply voltage or node capacitance, yet achieves additional reductions in dissipated energy by avoiding the single-rail DC power supply architecture. Adiabatic circuit's uses AC power supply to achieve low power consumption by maintaining small potential drops across conducting devices and by recycling the energy stored in output node capacitors during their operation. The low power digital circuits can be designed using adiabatic logic. Many DSP functional units such as FIR filters and FFT modules perform extensive sequences of multiplying and accumulating computations. In these applications multipliers are an important dissipation sources because they have high switching activity and contain large node capacitances. The adiabatic multiplier circuits can achieve a low power dissipation even in the presence of large load capacitance. An adiabatic 8-bit. Brent-Kung adder and 4-bit multiplier were implemented using CPAL and CMOS logic at 130nm. The power consumption of these circuits was observed for different frequencies up to 500MHz. The SPICE simulation results show that CPAL is efficient technique in terms of power consumption which has 35 to 75% less than CMOS counterparts depending on operating frequency and area needed for the design using CPAL is 20 to 25% more than the CMOS logic design