Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/11846
Title: DESIGN AND IMPLEMENTATION OF RECONFIGURABLE FLOATING POINT ARITHMETIC UNIT
Authors: Surekha, P. S.
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;RECONFIGURABLE FLOATING POINT ARITHMETIC UNIT;FPGA DESIGN;REAL-TIME SYSTEM
Issue Date: 2008
Abstract: In recent years computer applications have increased in their computational complexity. The industry wide usage of performance benchmarks such as SPECmarks forces processor designers to pay particular attention to implementation of the floating point unit or FPU. Special purpose applications such as digital signal processing, audio processing and many real time applications placed further demands on processors with floating point unit. Unfortunately, the huge hardware resources occupied by these floating-point arithmetic units make it difficult to house a large number of units in a single FPGA. In this work we present the partial reconfiguration technique for the implementation of floating point arithmetic unit (FP-A U) which makes FP-A U with less resource utilization and flexible to operate in a rapidly changing environment. The hardware resources occupied by this unit have been reduced through time-sharing them between modules. Partial reconfiguration is the ability of certain devices (FPGAs) to reconfigure only selected portions of their programmable hardware while other portions continue to operate undisturbed. A FPGA can be partially reconfigured using a partial bitstream. We can use such a partial bitstream to change the structure of one part of an FPGA design as the rest of the device continues to operate and this reduces the reconfiguration time
URI: http://hdl.handle.net/123456789/11846
Other Identifiers: M.Tech
Research Supervisor/ Guide: Joshi, R. C.
Saxena, A. K.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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