Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/11805
Title: DESIGN AND SIMULATION OF LOW JITTER PHASE LOCKED LOOP COMPONENTS
Authors: Paliwl, Abhishek
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;LOW JITTER PHASE LOCKED LOOP COMPONENTS;PHASE LOCKED LOOPS;DIGITAL SYSTEM
Issue Date: 2007
Abstract: Phase locked-loops (PLLs) are widely used as frequency synthesizer, clock recovery circuit and to generate well-timed on-chip clocks in high-performance digital systems, such as microprocessor. There are many issues while designing a complete PLL such as, to design for low power, high-speed, very high operating frequency, low jitter PLL, and low phase noise. Power supply or substrate noise perturb sensitive PLL components due to switching activity in a digital system, specifically Voltage controlled oscillator. Thus due to various noises present creates jitter in the output signal of PLL. Timing jitter significantly degrades the performance of the system. This research work intends to find out various Phase Locked Loop (PLL) components which generate least jitter, and design and simulate them using TSMC 0.35 ,um technology using tanner tools. Phase frequency detector PFD is designed using True Single Phase Clock (TSPC) D Flip-Flop; Voltage Control Oscillator (VCO) is designed using pseudo-differential CMOS ring structure. A noise canceling circuit is used to minimize supply induced noise since supply noise is major source of jitter in VCO. Typical tuning range of 100MHz to 800MHz is achieved, VCO consumes 1.44mW of power at 800MHz, the Charge Pump(CP) circuit designed has wide output range and no jump phenomenon. The power consumption of CP is 2.3mW.The features of above components that ensure least jitter are explained iii
URI: http://hdl.handle.net/123456789/11805
Other Identifiers: M.Tech
Research Supervisor/ Guide: Saxena, A. K.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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