DESIGN AND SIMULATION OF 4 BIT FLASH ADC IN 70nm TECHNOLOGY

Abstract

The analog to digital converters are the key components in modem electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. Nowadays, ADC becomes a part of the system on chip instead of stand alone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are developing day by day to achieve high performance ADCs. Of all types of ADCs, the Flash ADC is not only useful for its data conversion rate but also it becomes the part of other types of ADC for example Pipeline and multi bit Sigma Delta ADCs. The main problem with a Flash ADC is its power consumption and area, which doubles with every bit increase in resolution. In this dissertation, a 4 bit Flash ADC is designed and simulated in 70n.m CMOS technology using Tanner spice, which operates with a power supply of 0.7V and has an analog resolution of 33 mV and analog input range of 0.52V.The DNL and INL errors are in the acceptable range of 0.5 LSB.We realize this Flash ADC by designing a sample and hold circuit, and a low offset comparator. A thermometer to binary code converter is also realized.