RUNTIME SCALABLE POWER-AWARE BOOTH MULTIPLIER USING 2-DIMENSIONAL PIPELINE GATING

Abstract

Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Energy-efficient power-aware design is highly desirable for DSP functions that encounter a wide diversity of operating scenarios in battery powered wireless sensor network systems. The DSP functions extensively make use of the multiply-and-accumulate (MAC) operation, which makes the multiplication function as most power-consuming task. Therefore it is essential to implement the power-efficient multipliers for power-aware DSPs. Addressing power-awareness, a novel reconfigurable pipelined Booth multiplier using 2-dimensional pipeline gating scheme is proposed. This technique is to gate the clock to registers in both vertical direction (data flow direction in pipeline) and horizontal direction (within each pipeline stage). For signed multipliers using 2's complement representation, sign extension, which wastes power and causes longer delay, could be avoided by implementing this technique. Our multiplier based on the gated input signals implements a 16-bit, 8bit or 4-bit multiplication operation. The proposed reconfigurable pipelined Booth multiplier was first modeled in VHDL and functionally verifiedd using Mentor Graphics ModelSim simulator. After functional validation, the architecture was synthesized for appropriate time and area constraints using Synopsys Design Compiler. TSMC 90nm CMOS technology and standard cell library were used. The power analysis of the gate level structure was done using Synopsys VCS and PrimePower tool. For the 8-bit and 4-bit computations, the proposed Booth multiplier leads to a 61 % and 87% power consumption reduction over a non-scalable Booth multiplier, respectively. The proposed scalable pipelined Booth multiplier proves to be globally 48% more power efficient than a non-scalable pipelined Booth multiplier, and also it has fast speed due to pipelining.