IMPLEMENTATION OF LDPC DECODER

Abstract

Novel communication and information services are being introduced almost daily and the demand for higher data rates continues to grow. Error correcting codes insert redundancy into the transmitted data stream so that the receiver can detect and possibly correct errors that occur during transmission. This poses a challenge to find an optimal coding scheme that has good performance and can be efficiently implemented in hardware. The Low-Density Parity-Check (LDPC) codes are among the most powerful forward error correcting codes, since they enable to get as close as a fraction of a dB from the Shannon limit. This astonishing performance combined with their relatively simple decoding algorithm makes these codes very attractive for the digital communication systems. Inherent parallelism of the sum-product algorithm (used for decoding LDPC codes) makes it very suitable to implement on hardware platforms like field programmable gate array (FPGA). In this dissertation the modified sum-product algorithm is considered for implementation of LDPC decoder. The Quasi-cyclic LDPC codes which are more amenable to VLSI implementation are used. (8176, 7154) quasi-cyclic LDPC encoder is implemented which produces 1022 parity bits in the codeword. This codeword is decoded by the LDPC decoder which is synthesized using hardware description language