DESIGN OF A NEW DIGITAL PLL FREQUENCY SYNTHESIZER IN 0.18 Pm CMOS TECHNOLOGY WITH LOW LOCKING TIME

Abstract

Frequency Synthesis represents the key aspect of clocking in modern high-speed digital systems and -communication. When realized as a phase-locked loop (PLL), frequency synthesizers display high precision and allow simple implementation of programmable frequency switching. In conventional frequency synthesizer operating speed and frequency are limited by frequency divider and voltage-controlled oscillator (VCO). In this thesis, we propose an improved architecture of Digital PLL frequency synthesizer, which has a dual modulus prescaler divider with asynchronous cascaded divided-by-2 circuitry for higher switching speed. The focus is on the circuit configuration and performance parameters of the basic units of the Digital PLL: phase-frequency detector, charge pump, loop filter, voltage controlled oscillator (VCO) and programmable divider. Simulation results of the Digital PLL with a standard 0.18μm CMOS technology in SPICE illustrate a low locking time. The lock time can be modified by adjusting charge pump current and loop filter capacitor. The PFD (Phase Frequency Detector) circuit is also designed to prevent fluctuation of charge pump circuit under the locked condition. Design of the LPF (Low Pass Filter) involves analysis of loop dynamics of the PLL. Encapsulating various tradeoffs such as lock range, lock time and bandwidth, it is arguably the most challenging block to design. To have linear output frequency tuning range, large capacitance is required (i.e., large area). In order to increase frequency ranges without an increase chip area usage, this work describes a voltage-controlled oscillator (VCO) utilizing a ring of current-starved oscillator which provides linear variation of operating frequency range with supply voltage.