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|Title:||VHDL IMPLEMENTATION OF SINGLE-MASTER SINGLE-SLAVE IBC BUS CONTROLLER|
|Authors:||Bafna, saket Kumar|
|Keywords:||ELECTRONICS AND COMPUTER ENGINEERING;IBC BUS CONTROLLER;VHDL;MICROCONTROLLER|
|Abstract:||Microcontroller/Microprocessor use byte wide buses to accomplish communication with peripheral. This result in lots of copper tracks on PCB's to route the Address and data lines. Not to mention a bunch of address decoders and glue logic to connect everything. In mass production items such as TV-sets, VCR's and audio equipment this is not acceptable. The research done by Philips Labs in Eindhoven (The Netherlands) resulted in a 2-wire communication bus called the IPC bus. I2C performs chip-to-chip communications using only two wires in a serial interface, allowing ICs to communicate with fewer pins. These two wires carry addressing, selection, control, and data, one bit at a time. ICs that use the I2C bus can perform the same function as their larger parallel interface counterparts, but with far fewer pins. This greatly reduces the size and cost of ICs based on the I2C bus. How my work is better than previous one? Answer for this question is the PC is a microcode-free design developed for reuse in FPGA implementations means it can be burnt on FPGA kit and it gives a flexibility to change its protocol according to conditions and needs at real time. There is a special chip to do the PC interfacing. The PCD8584 or PCF8584 incorporate a complete I2C interface. These chips are designed in such way that they can interface to almost any microcontroller around but the major problem with this ICs are it can not change its protocols once it has been designed. VHDL is used as software synthesis tool for designing the processor. XILINX ISE (Integrated Software Environment) WEBPACK 6.1i software is used for this purpose. Basic units are described using behavioral programming and they are interconnected using structural programming to form complete I2C bus controller. To simulate MODSIM 5.4 simulator is used. Simulation is used to check the correctness of the design before placing the design for implementation. iii|
|Research Supervisor/ Guide:||Mhtra, R.|
|Appears in Collections:||MASTERS' DISSERTATIONS (E & C)|
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