Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/11714
Authors: Tiwari, Vivek
Issue Date: 2007
Abstract: An Arithmetic Logic Unit (AL U) is core of the datapath subsystem of any digital processor. This is where all the computations are performed. AL U design for next generation processors involves a wide range of constraints on its performance and power budgets and ultimately requires optimization of speed, power and area at every level of design implementation ranging from process, device, circuit, gate, architectural to algorithmic level. In this thesis, we have mainly focused our attention at circuit and gate level optimization. A 64-bit ALU has been designed at transistor level using Monotonic-Static CMOS (MS-CMOS) logic style with a feature size of 90nm. MS-CMOS is a low power, high speed logic family which can be seen as an intermediate logic design style between standard Static CMOS and Dynamic CMOS. It is particularly suitable for implementation of monotonic functions. Critical units of the ALU are designed using MS-CMOS logic while rest of the modules are implemented using static CMOS. The designed AL U operates at a frequency of 1.25 GHz with a dual supply of 1.2-0.6 Volt. A modified carry-lookahead adder is used in the ALU design which is considerably faster than ripple carry adder. Since Adder is the main performance bottleneck in the ALU design, the improved adder design reduces critical path delay and improves overall performance. Also, concept of. dual power supply is applied to reduce power consumption of whole circuit. Higher power supply (1.2V) is used to drive the arithmetic unit components which lie in the critical path whereas lower power supply (0. 6V) drives the logical unit. This saves nearly 75% of the power consumption in logical unit and accounts for more than 18% of the total power consumed in ALU. The designed ALU, performs basic arithmetic operations like addition, subtraction, increment, decrement, transfer and logical operations like AND, OR, XOR, NOT with logical, arithmetic and circular shifts in both direction. All the simulations are done in. T-Spice v9. 0 in 90nm technology. Model file used is based on the predictive ' technology model and with spice level-49 parameters provided in it.
Other Identifiers: M.Tech
Research Supervisor/ Guide: Saxena, A. K.
Dasgupta, S.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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