Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/11698
Title: :.N OF I/O BUFFER (SLEW RATE CONTROLLED) IN 90 nm CMOS'PROCESS
Authors: Verma, Vivek Raj
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;SLEW RATE CONTROLLED;CMOS PROCESS;COMMUNICATIONS
Issue Date: 2006
Abstract: The input/output (I/O) circuits are very essential to VLSI chip design. The design quality of these circuits is a critical factor that determines the reliability, signal integrity and inter chip communication speed of the chip in a systems environment. If the package is considered a protection layer of the silicon chip, then the UO frame containing input and output circuits can be considered a second protection layer. Any external hazards such as electrostatic discharge (ESD) and noises should be filtered out before propagating to the internal circuit for their protection. In the work carried out, various aspects of IO design has been studied and taken care of, specially from the point of slew rate control in the IOs. Basically the input/output buffers consists of Schmitt trigger, level shifter, multiplexer to select different modes, slew rate controller and a particular buffer which can drive a specified current level according to the load. Current slew is the rate of change of current w.r.t time di/dt. As the term indicates slew rate control means to "control" the output slew of the I/O buffer. As we have mentioned above UOs connects the CORE to the external world. The bonding wires of the pads (in the packaging) have a certain amount of inductance associated with it. This induces an undesirable (noise) voltage Ldi/dt. This noise is detrimental to the I/O performance and worse could cause functionality problems and should be kept low. To keep it low we have two options either to reduce L or to reduce di/dt. We have no control over the first factor from the design point of view so only thing which we can do is to "control" the slew. Normally the designing of an I/O is done in the worst case conditions i.e. meeting the timing constraints etc. Worst case design is used so that the data can be transferred from one circuit to another within a given time period. It is under these conditions that the slew is measured but unfortunately the worst case condition for the slew lies on the other end usually referred to as the "best conditions". Therefore as we move from towards the best conditions slew increases and degrades the noise performance. Active slew rate control is the way to compensate for this change of slew with the PVT conditions so as to able to keep relatively constant slew over all conditions which has been done in this design
URI: http://hdl.handle.net/123456789/11698
Other Identifiers: M.Tech
Research Supervisor/ Guide: Garg, Paras
Saxena, A. K.
Dasguta, S.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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