MERGING OF TIMING FOR DIFFERENT VOLTAGE CONDITIONS

Abstract

The I0 cell works on two voltages Vdd (supply voltage to core) and Vdde (supply voltage to pad). Now due to cascading the effect on input slope is minimal on timing delays. Today simulation results are provided corresponding to different voltages (where only Vdd changes but Vdde remains the same). It has been observed that when only Vdd changes but not Vdde, the simulation result for any other Vdd can be predicted with only small extra simulation. So we can exploit this property to extract the exact timings without simulation, hence saving lot of simulation time. Instead of doing the complete analysis on all the voltage conditions which consumes a lot of time, we can do complete characterization for one voltage condition and partial data for the second voltage condition and then based on this data, we can get the complete timing delays for all the voltage conditions without doing any simulation for the second voltage condition. The difference between the values obtained from simulation and the values obtained by timing merging is negligible and simulation time is also reduced to a greater extent (by almost 60%) which is the major benefit of this approach with negligible error. Two tools are used for this-Alto and Eldo, Alto is used to extract the process, voltage, temperature, slope, cload and netlist (which consists the device level information) and make .cir file (which consists the voltage signals applied to the pins) from which simulation is done by the Eldo tool to give .qa (consists the errors and the simulation time taken) and .rdb files (the results are written) as an output which will further be used to print the unidata after characterisation. The developed methodology has been tested on different libraries to check whether the error is minimal or not. The time taken for both the methodologies has been compared.