Please use this identifier to cite or link to this item: http://localhost:8081/jspui/handle/123456789/11678
Full metadata record
DC FieldValueLanguage
dc.contributor.authorReddy, J. Hari Krishna-
dc.date.accessioned2014-11-28T04:42:13Z-
dc.date.available2014-11-28T04:42:13Z-
dc.date.issued2006-
dc.identifierM.Techen_US
dc.identifier.urihttp://hdl.handle.net/123456789/11678-
dc.guideMisra, Manoj-
dc.description.abstractperformance, flexibility, and security. The requirements for performance and flexibility have sparked the emergence of network processors; while the requirement for security has driven the generality of various network security solutions such as firewalls. In this dissertation work, a stateful packet filtering firewall is implemented using IXP2800 Network Processor. This firewall implementation involves development of receive, packet filtering and transmitting modules on the fast-path microengines. These modules are developed using microC and executed by microengines. These modules are executed using both ordered and unordered thread execution strategies. The simulation results of this firewall implementation in both ordered and unordered thread execution is taken under different network loads and tuning parameters. The simulation results show that the unordered thread execution works better than the ordered thread execution. These results are also compared with the CISCO PIX Firewall 5 installed at IIT-Roorkeeen_US
dc.language.isoenen_US
dc.subjectELECTRONICS AND COMPUTER ENGINEERINGen_US
dc.subjectFIREWALT BUILTen_US
dc.subjectNETWORK PROCESSORen_US
dc.subjectEVALUATIONen_US
dc.titlePERFORMANCE EVALUATION OF FIREWALT BUILT USING A NETWORK PROCESSORen_US
dc.typeM.Tech Dessertationen_US
dc.accession.numberG12736en_US
Appears in Collections:MASTERS' THESES (E & C)

Files in This Item:
File Description SizeFormat 
ECDG12736.pdf2.1 MBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.