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| Issue Date | Title | Author(s) | Research Supervisor/ Guide | Type |
|---|---|---|---|---|
| 2007 | DESIGN OF A NEW DIGITAL PLL FREQUENCY SYNTHESIZER IN 0.18 Pm CMOS TECHNOLOGY WITH LOW LOCKING TIME | Agarwal, Vinit | Saxena, A. K.; Dwiviedi, S. | M.Tech Dessertation |
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