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Shodhbhagirathi @ IITR
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ELECTRONICS AND COMMUNICATION ENGINEERING (FORMERLY ELECTRONICS & COMPUTER ENGINEERING)
MASTERS' THESES (E & C)
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Results 1-10 of 15 (Search time: 0.006 seconds).
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Issue Date
Title
Author(s)
Research Supervisor/ Guide
Type
2007
DESIGN OF 1.25 GHz, DUAL SUPPLY, 64-BIT ALU USING MONOTONIC STATIC CMOS LOGIC
Tiwari, Vivek
Saxena, A. K.; Dasgupta, S.
M.Tech Dessertation
2008
DESIGN OF SWITCHED CAPACITOR BASED LOW PASS SIGMA DELTA MODULATOR
Patluri, Bindu
Saxena, A. K.; Dasgupta, S.
M.Tech Dessertation
2008
HARDWARE EFFICIENT DESIGN OF PARALLEL FIR FILTERS AND ITS APPLICATION TO 2D DWT
Kellampalli, Suresh
Dasgupta, S.
M.Tech Dessertation
2009
A COMPARATIVE STUDY OF 61, 8T AND 9T DECANANO SRAM CELL
athe, Paridhi
Dasgupta, S.
M.Tech Dessertation
2009
MODELLING OF CROSSTALK NOISE IN LOCAL INTERCONNECTS
Choudhury, Tapas
Dasgupta, S.
M.Tech Dessertation
2009
DESIGN AND SIMULATION OF CMOS BASED 16-BIT MICROPIPELINED ASYNCHRONOUS ANALOG TO DIGITAL CONVERTER (AADC) FOR LOW POWER APPLICATIONS
Bh, Maruthi Chandrasekhar
Dasgupta, S.
M.Tech Dessertation
2008
CPAL BASED DESIGN OF ARITHMETIC AND LOGIC CIRCUITS
Reddy, A. Rajasekhara
Dasgupta, S.
M.Tech Dessertation
2008
DESIGN OF LOW LEAKAGE HIGH PERFORMANCE MGDG BASED SRAM at 32nm TECHNOLOGY NODE
Kumar K., Venkata Komal
Joshi, R. C.; Dasgupta, S.
M.Tech Dessertation
2009
SINGLE EVENT UPSET TOLERANT D-FLIP FLOP DESIGN IN 90nm PDSOI TECHNOLOGY
Puvvala, Eswara Kumar
Dasgupta, S.
M.Tech Dessertation
2008
DESIGN OF DIGITAL CIRCUITS USING DTGAL, CPAL AND ACPL FOR LOW POWER APPLICATIONS
Sudhaeshan, Y. K.
Dasgupta, S.
M.Tech Dessertation
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Author
1
Puvvala, Eswara Kumar
1
Reddy, A. Rajasekhara
1
Sudhaeshan, Y. K.
1
Swetha, R.
1
Tiwari, Vivek
.
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15
ELECTRONICS AND COMPUTER ENGINEERING
2
CMOS LOGIC
2
CPAL
1
18ONM CMOS TECHNOLOGY
1
2-DIMENSIONAL PIPELINE GATING
1
2D DWT
1
4 BIT FLASH ADC
1
64-BIT ALU
1
ACPL
1
ADC DESIGN
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Date issued
6
2008
6
2009
3
2007
Research Supervisor/ Guide
2
Saxena, A. K.
1
Joshi, R. C.
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