Skip navigation
Home
Browse
Communities
& Collections
Browse Items by:
Issue Date
Author
Title
Subject
Research Supervisor/ Guide
Help
Sign on to:
My DSpace
Receive email
updates
Edit Profile
Shodhbhagirathi @ IITR
Search
Search:
All of DSpace
ELECTRONICS AND COMMUNICATION ENGINEERING (FORMERLY ELECTRONICS & COMPUTER ENGINEERING)
MASTERS' THESES (E & C)
for
Current filters:
Title
Author
Subject
Date Issued
Research Supervisor/ Guide
Has File(s)
???jsp.search.filter.original_bundle_filenames???
???jsp.search.filter.original_bundle_descriptions???
Equals
Contains
ID
Not Equals
Not Contains
Not ID
Title
Author
Subject
Date Issued
Research Supervisor/ Guide
Has File(s)
???jsp.search.filter.original_bundle_filenames???
???jsp.search.filter.original_bundle_descriptions???
Equals
Contains
ID
Not Equals
Not Contains
Not ID
Title
Author
Subject
Date Issued
Research Supervisor/ Guide
Has File(s)
???jsp.search.filter.original_bundle_filenames???
???jsp.search.filter.original_bundle_descriptions???
Equals
Contains
ID
Not Equals
Not Contains
Not ID
Title
Author
Subject
Date Issued
Research Supervisor/ Guide
Has File(s)
???jsp.search.filter.original_bundle_filenames???
???jsp.search.filter.original_bundle_descriptions???
Equals
Contains
ID
Not Equals
Not Contains
Not ID
Start a new search
Add filters:
Use filters to refine the search results.
Title
Author
Subject
Date Issued
Research Supervisor/ Guide
Has File(s)
???jsp.search.filter.original_bundle_filenames???
???jsp.search.filter.original_bundle_descriptions???
Equals
Contains
ID
Not Equals
Not Contains
Not ID
Results 11-20 of 21 (Search time: 0.014 seconds).
previous
1
2
3
next
Item hits:
Issue Date
Title
Author(s)
Research Supervisor/ Guide
Type
2009
HIGH PERFORMANCE ADVANCE ENCRYPTION STANDARD IMPLEMENTATION ON FPGA
Patel, Vishwanath
Joshi, R. C.; Saxena, A. K.
M.Tech Dessertation
2008
DESIGN AND IMPLEMENTATION OF RECONFIGURABLE FLOATING POINT ARITHMETIC UNIT
Surekha, P. S.
Joshi, R. C.; Saxena, A. K.
M.Tech Dessertation
2009
DESIGN OF LOW POWER DIGITAL CIRCUITS AND REGISTER FILE USING ADIABATIC COMPLEMENTARY PASS-TRANSISTOR LOGIC
Daravathu, Sreenu
Saxena, A. K.
M.Tech Dessertation
2006
MERGING OF TIMING FOR DIFFERENT VOLTAGE CONDITIONS
Priya, V. Lakshmi
Goyal, vishal; Saxena, A. K.; Dasguta, S.
M.Tech Dessertation
2002
TRANSPORT PROPERTIES OF TRANSITION METAL DOPED INDIUM PHOSPHIDE
Kumar, Shailesh
Saxena, A. K.
M.Tech Dessertation
2007
DESIGN OF A NEW DIGITAL PLL FREQUENCY SYNTHESIZER IN 0.18 Pm CMOS TECHNOLOGY WITH LOW LOCKING TIME
Agarwal, Vinit
Saxena, A. K.; Dwiviedi, S.
M.Tech Dessertation
2007
FPGA IMPLEMENTATION OF MEMORY-SPEED OPTIMIZED ARCHITECTURE OF 2-D DWT FOR IMAGE COMPRESSION APPLICATIONS
Bansal, Sudhakar
Saxena, A. K.
M.Tech Dessertation
2009
DESIGN AND SIMULATION OF 32 BIT ALU BASED ON FEEDBACK SWITCH LOGIC
Prakash, Patanjali
Saxena, A. K.
M.Tech Dessertation
2007
DESIGN AND SIMULATION OF LOW JITTER PHASE LOCKED LOOP COMPONENTS
Paliwl, Abhishek
Saxena, A. K.
M.Tech Dessertation
2007
DESIGN OF OP-AMP FOR ANALOG TO DIGITAL CONVERTERS
Bojedla, Naresh Babu
Saxena, A. K.
M.Tech Dessertation
Discover
Author
1
Agarwal, Vinit
1
Bansal, Sudhakar
1
Bojedla, Naresh Babu
1
Daravathu, Sreenu
1
Gaddam, Srinivas
1
Gupta, Abhay
1
Kahatri, Bhunesh Singh
1
Kumar, Amit
1
Kumar, Hitendra
1
Kumar, K. Prashanth
.
next >
Subject
2
GALLIUM ARSENIDE
2
IMAGE COMPRESSION
1
64-BIT ALU
1
ADIABATIC COMPLEMENTARY
1
ALU BASED
1
ALUMINUM GALLIUM ARSENIDE
1
ANALOG TO DIGITAL CONVERTERS
1
ANALYSIS-MODELING-TEMPERATURE
1
ARITHMETIC UNITS
1
CAPACITOR
.
next >
Date issued
5
2007
5
2008
4
2009
3
2006
1
2001
1
2002
1
2004
1
2005
Research Supervisor/ Guide
4
Joshi, R. C.
2
Dasgupta, S.
2
Dasguta, S.
1
Dwiviedi, S.
1
Garg, Paras
1
Goyal, vishal
1
Gupta, S. das