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| Issue Date | Title | Author(s) | Research Supervisor/ Guide | Type |
|---|---|---|---|---|
| 2012 | PERFORMANCE ANALYSIS OF CARBON NANOTUBE BASED INTERCONNECT | pandya, Nisarg D. | Kaushik, B. K.; Manhas, S. K. | M.Tech Dessertation |
| 1996 | SWITCH-LEVEL DELAY SIMULATOR FOR CMOS CIRCUITS | Jangir, Hari Narayan | Kumar, Padam | M.Tech Dessertation |
| 1986 | ON DESIGNING TESTABLE BIT-SLICE ARCHITECTURE | Gupta, Devendra Kumar | Rai, Suresh | M.Tech Dessertation |
| 2000 | A STUDY OF VLSI INTERCONNECT DELAY MINIMIZATION USING CMOS-REPEATERS | Bisht, Rajani | Sarkar, S.; Agarwal, R. P. | M.Tech Dessertation |
| Jun-2013 | 3-DIMENSIONAL SIMULATION OF SINGLE EVENT UPSET OF 6T-SOI BASED 24 nm —FINFET SRAM CELL | Jayaram, Namani | - | M.Tech.-Thesis |