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Issue Date | Title | Author(s) | Research Supervisor/ Guide | Type |
---|---|---|---|---|
2007 | DESIGN OF 1.25 GHz, DUAL SUPPLY, 64-BIT ALU USING MONOTONIC STATIC CMOS LOGIC | Tiwari, Vivek | Saxena, A. K.; Dasgupta, S. | M.Tech Dessertation |
2007 | DESIGN OF A NEW DIGITAL PLL FREQUENCY SYNTHESIZER IN 0.18 Pm CMOS TECHNOLOGY WITH LOW LOCKING TIME | Agarwal, Vinit | Saxena, A. K.; Dwiviedi, S. | M.Tech Dessertation |
2007 | FPGA IMPLEMENTATION OF MEMORY-SPEED OPTIMIZED ARCHITECTURE OF 2-D DWT FOR IMAGE COMPRESSION APPLICATIONS | Bansal, Sudhakar | Saxena, A. K. | M.Tech Dessertation |
2007 | DESIGN AND SIMULATION OF LOW JITTER PHASE LOCKED LOOP COMPONENTS | Paliwl, Abhishek | Saxena, A. K. | M.Tech Dessertation |
2007 | DESIGN OF OP-AMP FOR ANALOG TO DIGITAL CONVERTERS | Bojedla, Naresh Babu | Saxena, A. K. | M.Tech Dessertation |
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