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Shodhbhagirathi @ IITR
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ELECTRICAL ENGINEERING
MASTERS' THESES (Electrical Engg)
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Issue Date
Title
Author(s)
Research Supervisor/ Guide
Type
2004
OPTIMAL SIZING AND LOCATION OF CAPACITOR BANK FOR POWER DISTRIBUTION SYSTEMS
Jhanwar, Nitin
Gupta, Hari Om; Gupta, Indra
M.Tech Dessertation
2009
CHIP ARCHITECTURE FOR DATA SORTING USING RECURSIVE ALGORITHM
Agarwal, Megha
Gupta, Indra
M.Tech Dessertation
2006
DYNAMIC RESPONSE OF FIELDBUS BASED PROCESS CONTROL SYSTEM
Das, Gautham P.
Pillai, G. N.; Gupta, Indra
M.Tech Dessertation
2002
A REDUCED ORDER MODEL SIMULATION FOR DISTILLATION COLUMN
Khatri, Navita
Pant, A. K.; Gupta, Indra
M.Tech Dessertation
2002
POWER DISTRIBUTION IN COMPETITIVE POWER MARKET
Kolaskar, Trupti
Gupta, Hari Om; Gupta, Indra
M.Tech Dessertation
2006
FPGA BASED FLOATING POINT PROCESSOR
Prabhu, Sanjay
Vasantha, M. K.; Gupta, Indra
M.Tech Dessertation
2009
CLOSED LOOP OFDM SYSTEMS
Phaneedra, P. V. S.
Gupta, Indra
M.Tech Dessertation
2009
FAULT CLASSIFICATION AND LOCATION IN SERIES COMPENSATED LINE USING SVM
Tripathi, Pushkar
Pillai, G. N.; Gupta, Indra
M.Tech Dessertation
2006
IMPLEMENTATION OF FIR FILTER IN FPGA
Kumar, Devara Dilip
Vasantha, M. K.; Gupta, Indra
M.Tech Dessertation
2006
IMPLEMENTATION OF MPEG SYSTEM FOR IMAGE PROCESSING USING FPGA
Tak, Prashant
Vasantha, M. K.; Gupta, Indra
M.Tech Dessertation
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Author
1
Agarwal, Megha
1
Chandramouly, Vengala
1
Das, Gautham P.
1
Gulati, Puneet
1
Jhanwar, Nitin
1
Khatri, Navita
1
Kolaskar, Trupti
1
Kumar, Devara Dilip
1
Kundu, Parveen
1
Mane, Pravin Sakharam
.
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Subject
4
FPGA
3
DISTILLATION COLUMN
1
16 - BIT RISC PROCESSOR DESIGN
1
ANN BASED ESTIMATOR
1
BINARY DISTILLATION PROCESS
1
CAPACITOR BANK
1
CHIP ARCHITECTURE
1
CLOSED LOOP OFDM SYSTEMS
1
COMPETITIVE POWER MARKET
1
DATA SORTING
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Date issued
5
2006
3
2009
2
2002
2
2004
2
2005
1
2000
Research Supervisor/ Guide
7
Vasantha, M. K.
2
Gupta, Hari Om
2
Pillai, G. N.
1
Pant, A. K.