Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/11494
Title: IMPLEMENTATION OF IMAGE ENHANCEMENT TECHNIQttES ON FPGA
Authors: Mavireddy, Sridhar
Keywords: ELECTRICAL ENGINEERING;IMAGE ENHANCEMENT TECHNIQUES;FPGA;MULTI SCALE MORPHOLOGICAL CONTRAST ENHANCEMENT TECHNIQUE
Issue Date: 2010
Abstract: The main aim of this dissertation is to implement various image enhancement techniques on FPGA. Image enhancement is a technique for improving the perception of image so that it can be easily observed. Multi scale Morphological Contrast Enhancement technique for different sizes structuring elements are successfully implemented on FPGA. Processing of the image can be done by processing it pixel by pixel. For, hardware implementation, the image is converted into ID signal which represents amplitude signal of image with respect to time. Each time unit represents an index of pixel in the image. For point processing applications, the serial input can be directly given to FPGA, because processing does not depend on surrounding pixels. In spatial techniques, processing of a pixel depends on surrounding pixels. A mechanism to buffer the surrounding pixels is implemented using line buffers. The design for processing the image is implemented with the help of Xilinx Tools. Both designs are implemented in system generator.
URI: http://hdl.handle.net/123456789/11494
Other Identifiers: M.Tech
Research Supervisor/ Guide: Kumar, Vinod
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (Electrical Engg)

Files in This Item:
File Description SizeFormat 
EEDG20392.pdf5.28 MBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.