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|Title:||IMPLEMENTATION OF IEEE 1451.3 COMPLIANT TBIM AND TBC ON FPGA|
|Keywords:||ELECTRICAL ENGINEERING;IEEE 1451.3 COMPLIANT TBIM;TBC;FPGA|
|Abstract:||With the need of increasing measurement and control units, that is automation, in the industry, the need of standardized software and hardware related to the measurement and control components and their interface is being increasingly felt. The IEEE-1451 set of standards, which regulate the development of the smart systems, is a complete and comprehensive set of standards that defines architectures which allow smart sensors and actuators connection to an existing distributed measurement and control network in different situations. For this purpose, one processor acts as an intermediate processor between the smart transducer (sensor or actuator) and the existing network, and is called Network Capable Application Processor (NCAP). In this work the smart transducer and the communication interface of the smart transducer network interface will be implemented on the VHDL platform as defined in IEEE 1451.3 standards. The IEEE 1451.3 standard introduces the concept of a Transducer Bus Interface Module (TBIM) and a Transducer Bus Controller (TBC) connected by a transducer bus. A TBC is the hardware and software in the NCAP or host processor that provides the interface to the transducer bus. A TBIM is a module that contains the bus interface, signal conditioning, Analog-to-Digital and/or Digital-to-Analog conversion and in many cases the transducers also. The TRIM is directly connected to the transducers. A Transducer Electronic Data Sheet (TEDS) is also stored in the transducers or memory for giving self identifying and self calibration capability as required by the standard. UART is taken as the communication interface for the communication between the transducer and the processor. The work is physically implemented on an Spartan-3E FPGA Starter kit, as this development kit giving designers instant access to the capabilities of the Spartan-3E family FPGA. The actual outputs of the implemented module are as per the design and conform to the IEEE 1451.3 standard.|
|Research Supervisor/ Guide:||Verma, H. K.|
|Appears in Collections:||MASTERS' THESES (Electrical Engg)|
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