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|dc.description.abstract||The main aim of this dissertation is to implement various image enhancement techniques on FPGA. Image enhancement is a technique for improving the perception of image so that it can be easily observed. Two image enhancement techniques namely Morphological Contrast Enhancement technique and Kuwahara Edge Preserving Image Enhancement techniques are successfully implemented on FPGA. Processing of the image can be done by processing it pixel by pixel. For, hardware implementation, the image is converted into 1D signal which represents amplitude signal of image with respect to time. Each time unit represents an index of pixel in the image. For point processing applications, the serial input can be directly given to FPGA, because . processing does not depend on surrounding pixels. In spatial techniques, processing of a pixel depends on surrounding pixels. A mechanism to buffer the surrounding pixels is implemented using line buffers. The design for processing the image is implemented with the help of Xilinx Tools. Both designs are implemented in system generator. RTL design of one algorithm is developed using Verilog HDL.||en_US|
|dc.subject||IMAGE ENHANCEMENT TECHNIQUES||en_US|
|dc.subject||IMAGE ENHANCEMENT TECHNIQUE||en_US|
|dc.title||IMPLEMENTATION OF IMAGE ENHANCEMENT TECHNIQUES ON FPGA||en_US|
|Appears in Collections:||MASTERS' THESES (Electrical Engg)|
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