MIXED-SIGNAL IC DESIGN FOR TESTABILITY

Abstract

With a great growing use of electronic products in many aspects of society, it is evident that these products must perform reliably. Their reliability depends on the testing whether or not they have been manufactured properly and behave correctly. So there should be a post-production testing to verify their performance. During the fabrication process there may be defects in silicon which contribute towards the errors introduced in the physical device. Of course a chip will not work as per the specifications if there are any errors introduced in the production process.. Chip manufacturing companies are producing millions of chips everyday. Since, to run all the functional tests on each of the millions of chips produced or manufactured, is very time consuming, there is a need to devise some method, which can make users believe without running full exhaustive tests on the physical device, that the device has been manufactured correctly. The solution to the above problem is Design for Testability (DFT), defined as a design technique, which facilitates a device to become testable after production. It is the extra logic which is put in the normal design, during the design process, which makes its post-production testing easier and shorter. Now-a-days there are various DFT techniques like Scan Chain, Boundary Scan and Built-In Self Test (BIST) which have been developed for the testing of digital, analog and mixed-signal circuits. Among all the DFT techniques, BIST has become most popular because of its advantages like lower cost of test,' larger fault coverage, shorter test time and easier customer support. It is now common to see complex devices that have functionally diverse blocks built on different technologies inside them with a built-in test circuit, i.e. GIST. BIST follows simple testing rule which is applying automatically generated test patterns and observing the output response of the circuit under test. These test patterns should ideally ensure 100% fault coverage. There are several algorithms which have been developed to generate random (non-deterministic) or deterministic test patterns. Random test pattern generation algorithms do not guarantee 100% fault coverage, whereas the deterministic test pattern generation algorithms are having better fault coverage (100% stuck-at fault coverage). A program to implement deterministic test iv pattern generation algorithm is written in `C' language and reported in the present dissertation. In the present work, a basic architecture of BIST is modified and improved in respect of extra pins for BIST purpose. The modified architecture which adds only two extra pins to the IC package has been implemented for combinational, sequential, analog and mixed-signal circuits in MATLAB®. A quad XOR gate IC (7486) has been taken as example of combinational circuit and redesigned incorporating BIST facility. For the sequential circuit, a 4-bit binary counter IC (7493) has been chosen and modified the circuit to make it self-testable in non-scan style. Generally scan technique. is used for sequential circuits, which is found to be having some drawbacks like long test time and large overhead. For each implementation, the responses of both healthy and faulty circuit under test are shown. In case of digital circuits (both combinational and sequential), the test time is short because of the fact that it needs a small number of test patterns to achieve large fault coverage. Although tremendous developments have been achieved in digital circuit testing and there are several techniques available; but in the field of analog/mixed-signal circuits, it still in primitive stage. Some of the concepts and the techniques used in digital circuit testing have been applied in testing of analog/mixed-signal circuits in the present work. The same BIST architecture has been implemented for a quad op-amp IC (LM324) in two ways: first, considering fault at op-amp level and second, at transistor level. This concept has also been applied to mixed-signal circuits. Implementations have been done for both a 4-bit ADC and a 4-bit DAC. In case of analog/mixed-signal circuit, the test time is longer than that for digital circuits because of its requirement of long test patterns.