Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/11319
Authors: Kumar, Dhirendra
Issue Date: 2009
Abstract: In this Dissertation PID Controller scheme was suggested and implemented on FPGA using Matlab/Simulink. -System Generator-9.2 in Xilinx 9.2i environment. Based on Velocity Algorithm the block diagram to be implemented on FPGA was obtained, the blocks developed in different stages for implementing the block diagram were:- • Multiplier • Adder • Subtractor For designing, "Paper-and-Pencil Shift - and-Add Algorithm" for unsigned numbers multiplications with a few modification was designed for developing the Two's complement Parallel multiplier. Multiplier block has certain limitations in its output. The two's complement parallel multiplier was considered for final results. To design the PID control three approaches has been considered in this work. The first approach is continuous time approach, second is system generator block set approach and third one is the parallel multiplier approach. With the implementation of Parallel PID Controller, the rise time, settling time and the time required to recover from the disturbances significantly improve as compared to the System Generator Blocks based PID controller approach. Time required to recover from the disturbance was appreciable low in parallel PID controller approach as compared to Continuous Time PID Approach. To test the developed design, the Spartan 3e XC2S200-5Q208 FPGA from Xilinx environment has been used in the work. Simulation testing of the developed design has been carried on for the load disturbance control of a DC Motor.
Other Identifiers: M.Tech
Research Supervisor/ Guide: Tyagi, Barjeev
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' THESES (Electrical Engg)

Files in This Item:
File Description SizeFormat 
EEDG14483.pdf8.64 MBAdobe PDFView/Open

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.