IMPLEMENTATION OF IEEE 1451.4 MIXED-MODE COMMUNICATION PROTOCOL AND TEDS USING FPGA AND FPAA

Abstract

Sensor/Transducer networking is a fast growing technology. Networked transducers offer many advantages to users. Today multiple control and sensor networking solutions are emerging, each requiring a separate and significant effort on the part of transducer manufacturers. It is too costly for transducer manufacturers to make unique smart transducers for each network available in the market. Therefore, a universally accepted transducer interface standard, the IEEE 1451 standard, has been evolved. The family of IEEE 1451 standards provide a common interface and enabling technology for the connectivity of transducers to microprocessors, control and field networks and data acquisition and instrumentation systems. The 1451 standard contains seven sub-standards (1451.1-1451.7). In this work, the implementation of IEEE 1451.4 has been reported. The standard includes the mixed-mode communication protocol and TEDS (Transducer Electronic Data Sheet). TEDS add self-identification capability to transducers. An IEEE 1451.4 compliant transducer has TEDS embedded within the transducer itself. To make a traditional sensor IEEE 1451.4 compatible, TEDS can be added externally by writing them to an EEPROM according to the one-wire protocol defined in the standard. sing the reconfiguration capabilities of FPAA and FPGA, the implementation of IEEE 1451.4, a standard for smart transducer interface for sensors and actuators has been reported in this work. The required analog interface has been implemented on FPAA. The analog conditioned output from FPAA is converted to digital so that FPGA can reconfigure it dynamically. TEDS have been implemented on one-wire EEPROM chip using the One-Wire Viewer software provided by Maxim. To eliminate CPU bit-banging, a One-Wire bus master, which generates 1-wire timing and control signals, has been developed on FPGA. The software simulation for the same has been done and the results have been discussed. The reconfigurability of FPGA and FPAA devices allow for a large interface flexibility with an unique hardware design.