Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/11296
Authors: T. D., Manoj Vardhan
Issue Date: 2008
Abstract: Image Enhancement is a wide area with its applications in different domains. Image Enhancement is a computational intensive task; in which processing involves applying a specific function repetitively. One solution to carry out these computational intense tasks is to use a general purpose microprocessor or Digital Signal processor. But these implementations are sequential, with less on-chip memory for buffering, so we require external memory for buffering. Fetching data from this external memory require certain clock cycles which effects system performance. Also these systems require glue logic for their operations. We can reduce this glue logic and speed up our operations using Application Specific Integrated Circuits (ASICs). But main problem with ASICs are they require large' time to market and initial investments are high. Before developing an ASIC we require to prototype our design. Field programmable Gate Arrays (FPGAs) prove to be a better solution for rapid prototyping. FPGAs are reprogrammable, have large number of logic cells suitable for implementing image enhancement applications. We can explore the parallelism and pipelining feature of FPGA. The objective of this dissertation is design, modeling, simulation and synthesis of various Image Enhancement techniques. The dissertation aims in developing a prototype of Image enhancement processor. Initially, different Algorithms are studied and their hardware circuits are realized. Then these hardware blocks are coded using a suitable Hardware Descriptive language and simulated in a simulator to verify their functionality. Then this hardware logic is modeled in Matlab Simulink using Xilinx System generator Blockset and synthesized on Spartan3E xc3s500e-4fg320 FPGA chip. Then using hardware co-simulation feature of Spartan-3E starter kit, the results obtained in software and hardware simulations (i.e. on FPGA kit), are validated.
Other Identifiers: M.Tech
Research Supervisor/ Guide: Kumar, Vinod
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' THESES (Electrical Engg)

Files in This Item:
File Description SizeFormat 
EEDG13684.pdf4.62 MBAdobe PDFView/Open

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.