Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/11287
Authors: Prabhu, Sanjay
Issue Date: 2006
Abstract: In the present dissertation an FPGA based floating point processor (FPP) is developed and the methodology to attach it as a coprocessor any soft-core central processing unit (CPU) is presented. This assists CPU in computing the floating point operations. FPP as a coprocessor in system-on-programmable-chip (SoPC) environment directly replaces C software functions, by equivalent and faster hardware to accelerate the system performance considerably. The dissertation is divided into two parts: The first part consists of designing the algorithms for the hardware modules of FPP. The designed algorithms for the FPP hardware modules are dedicated to Alters devices, such that it 'allows save silicon space in any Altera device. The FPP hardware modules include data registers, status register, control register, tag register and arithmetic unit. The designed FPP arithmetic unit supports addition, subtraction, multiplication, division, comparison, square-root, absolute value, round to integer and change sign of a number. FPP input/output number format is according to IEEE-754 standard single precision real numbers. Internally, FPP calculations are performed according to IEEE-754 standard extended double precision real numbers (as incorporated in Intel Pentium processor). This inherited feature assists FPP in enhancing the accuracy. The second part consists of attaching the designed FPP as a coprocessor to Altera's Nios II soft-core processor through SoPC Builder. This part also consists of designing the Hardware Abstraction Layer (HAL) device driver for the designed FPP. FPP can be programmed in the Nios Integrated Development environment (IDE) through the defined customized macros in the HAL device driver. In the present work, Altera's SoPC design development kit and required CAD tools are used. The Altera Corporation UP3 kit used contains Cyclone Field Programmable Gate Array (FPGA) having 5980 logic elements. The synthesis, translate, mapping, place and route to program the FPGA are done using the Altera Quartus-Ii v5.0 standard CAD tool. The soft processor (Altera's Nios II v3.0) core has been configured using Graphical User interface (GUI) friendly SoPC Builder of Altera. SOPC Builder outputs a configured processor core in the form of a Hardware Descriptive Language (HDL) file and then this file is used, together with HDL file 'FPP (user-defined logic) and other peripherals, for synthesis through standard CAD tools. The C/C++ design codes targeted for the soft-core processor are compiled in Nios II IDE. The obtained results are tested and compared with C software function in NIOS IDE. Finally, the design methodology, experiences from the design process and issues encountered are discussed. i
Other Identifiers: M.Tech
Research Supervisor/ Guide: Vasantha, M. K.
Gupta, Indra
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' THESES (Electrical Engg)

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