Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/10238
Title: MAKING COMPUTERS FASTER USING VEDIC MATHEMATICS
Authors: Saroha, Ashok Kumar
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;VEDIC MATHEMATICS;HARDWARE CIRCUIT;COMPUTER SPEED
Issue Date: 1993
Abstract: Constant efforts and desire to achieve perfection is the essence of history of development of mankind. In the field of computers, the game has been to make computation speed faster and faster. For fulfilment of this goal, Scientists and Engine-ers have been exploring every possible angle and every possible source. In this dissertation, it has been shown that, Vedic Mathematics is a potential source to be exploited for making computers faster. The design and implementation of hardware circuits (which incorporate some of the sixteen Sutras from Vedic Mathematics) for multiplication and squaring has been elaborated. Speed of these circuit arrangements has been comp-ared with presently used algorithms and it is shown that speed, by using Vedic Mathematics Sutras, has certainly increased. In case of division, an algorithm has been developed by using another Sutra of Vedic Mathematics. This algorithm is a special case algorithm and is most suitable for divisions when divisor involves bigger digits. Implementation of this algorithm has been shown through software as well as hardware. Vedic Mathematics makes calculations faster and easier by taking advantage of certain practical characteristics of numbers. As shown in this work, some of these Vedic techniques (i.e. Sutras and Sub-sutras) can be usefu in increasing speed of computer.
URI: http://hdl.handle.net/123456789/10238
Other Identifiers: M.Tech
Research Supervisor/ Guide: Singh, Kuldip
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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