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http://localhost:8081/xmlui/handle/123456789/10231Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Rao, N. Narasimha | - |
| dc.date.accessioned | 2014-11-23T08:52:17Z | - |
| dc.date.available | 2014-11-23T08:52:17Z | - |
| dc.date.issued | 1991 | - |
| dc.identifier | M.Tech | en_US |
| dc.identifier.uri | http://hdl.handle.net/123456789/10231 | - |
| dc.guide | Gupta, J. P. | - |
| dc.description.abstract | This dissertation work studies the performance of GM20[28J C-DAC'S (Centre for Development of Advanced Computing India), Proposed i860 based message passing MIMD (Multiple Instructions and Multiple Data) computer. Two general Parallel Numerical algorithms, LU Decomposition and Matix multiplication were implemented on a 64 node GM20 Architecture Simulator. Sequential algorithms of these two methods and QR factorizations were implementated on Scalar and Vector modes of i860 Processor. The performance and the Speedup between the single processor and 64 processors, and between scalar and vector modes of one Processor are presented. | en_US |
| dc.language.iso | en | en_US |
| dc.subject | ELECTRONICS AND COMPUTER ENGINEERING | en_US |
| dc.subject | MESSAGE PASSING | en_US |
| dc.subject | PERFORMANCE EVALUATION | en_US |
| dc.subject | C-DAC | en_US |
| dc.title | PERFORMANCE EVALUATION OF 1860 BASED MESSAGE PASSING MULTICOMPUTER | en_US |
| dc.type | M.Tech Dessertation | en_US |
| dc.accession.number | 246366 | en_US |
| Appears in Collections: | MASTERS' THESES (E & C) | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| ECD246366.pdf | 2.51 MB | Adobe PDF | View/Open |
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