1. Shodhbhagirathi @ IITR
  2. ELECTRONICS AND COMMUNICATION ENGINEERING (FORMERLY ELECTRONICS & COMPUTER ENGINEERING)
  3. MASTERS' THESES (E & C)
Please use this identifier to cite or link to this item: http://localhost:8081/jspui/handle/123456789/10231
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dc.contributor.authorRao, N. Narasimha-
dc.date.accessioned2014-11-23T08:52:17Z-
dc.date.available2014-11-23T08:52:17Z-
dc.date.issued1991-
dc.identifierM.Techen_US
dc.identifier.urihttp://hdl.handle.net/123456789/10231-
dc.guideGupta, J. P.-
dc.description.abstractThis dissertation work studies the performance of GM20[28J C-DAC'S (Centre for Development of Advanced Computing India), Proposed i860 based message passing MIMD (Multiple Instructions and Multiple Data) computer. Two general Parallel Numerical algorithms, LU Decomposition and Matix multiplication were implemented on a 64 node GM20 Architecture Simulator. Sequential algorithms of these two methods and QR factorizations were implementated on Scalar and Vector modes of i860 Processor. The performance and the Speedup between the single processor and 64 processors, and between scalar and vector modes of one Processor are presented.en_US
dc.language.isoenen_US
dc.subjectELECTRONICS AND COMPUTER ENGINEERINGen_US
dc.subjectMESSAGE PASSINGen_US
dc.subjectPERFORMANCE EVALUATIONen_US
dc.subjectC-DACen_US
dc.titlePERFORMANCE EVALUATION OF 1860 BASED MESSAGE PASSING MULTICOMPUTERen_US
dc.typeM.Tech Dessertationen_US
dc.accession.number246366en_US
Appears in Collections:MASTERS' THESES (E & C)

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