DESIGN OF AN ASIC FOR 16 BIT ARITHMETIC UNIT USING GATE ARRAYS

Abstract

This dissertation covers the design of an Application Specific Integrated Circuit , for a 16 bit arithmetic unit, using gate arrays. The design work has been carried out, on NEXUS-3500 CAE workstation. The ASIC design pakage used, is MENTOR GRAPHICS IDEA SERIES, version 7, along with gate array library, from GOULD INC., USA. This dissertation work includes the detailed study of ASIC design process using gate arrays, properties of gate arrays, advantages and limitations of using gate array based ASICs. The process of designing an ASIC using gate arrays is discussed with particular reference to MENTOR GRAPHICS software. This 16 bit arithmetic unit, is intended to be used with 8 bit CPUs, for doing the 16 bit integer addition, subtraction, multiplication and 32 bit by 16 bit division. 8 bit CPUs do these calculations, normally using software algorithms or by using arithmetic coprocessors. The software implementation is usually slow; requiring hundreds of milli seconds typically. Arithmetic coprocessors are very costly and in general include so many unwanted functions also. This unit has been designed to do the four basic arithmetic functions only, for those applications that don't require the trignometric functions. This is implemented in a gate array based ASIC, to keep the price low. This I` unit can do the 16 bit, unsigned integer, multiplication and division, in approximately 5' micro seconds, including the time to load the operands and to read the results, much faster than any of the software algorithms. Complete circuit diagram, design report including design statistics, simulation results and the chip layout design, have been included as part of this report.