http://localhost:8081/jspui/handle/123456789/9 Sun, 19 Apr 2026 14:39:42 GMT 2026-04-19T14:39:42Z http://localhost:8081/jspui/handle/123456789/20403 Title: INVESTIGATIONS ON HIGH-POWER SUB-TERAHERTZ GYROTRONS Authors: Mondal, Debasish Abstract: Thermonuclear fusion holds significant potential as a feasible approach for the development of clean and sustainable green energy source to address the ever-expanding global energy demands. However, this ambitious endeavor is accompanied by significant technical obstacles. The initiation of a fusion reaction necessitates extreme temperatures inside the reactor, reaching around 150 million Kelvin. This extreme condition is required for the confinement of plasma and the sustained ignition of fusion reactions. Within the domain of plasma fusion experiments, Electron Cyclotron Resonance Heating and Current Drive (ECRH&CD) have emerged as the most efficient methods for heating magnetically confined plasmas. Gyrotrons have become vital components in experimental tokamaks, primarily because of their ability to generate powerful millimeter and sub-THz waves. These devices play a crucial role in applications related to ECRH&CD. These devices are capable of generating power ranging from several hundred kilowatts to multiple megawatts. The importance of these devices is emphasized by their incorporation into state-of-the-art fusion tokamaks (machines that confine plasma), such as the International Thermonuclear Experimental Reactor (ITER), ASDEX-Upgrade, DIII-D, EAST, KSTAR, and W7-X stellarator. Particularly, W7-X stellarator showcases the implementation of ten gyrotrons, each capable of providing an impressive 1MW of continuous wave (CW) power at a frequency of 140 GHz, specifically for plasma heating. Furthermore, a pioneering endeavor is currently underway to install the first batch of 24CW gyrotrons, each capable of delivering 1MW of power at 170 GHz, to support plasma heating in the ITER tokamak located in Cadarache, France. The ITER project is a significant endeavor with the aim of validating nuclear fusion as a viable commercial, large-scale, and clean energy production method, aspiring to generate a remarkable 500MWof electrical power while ensuring the stable confinement of fusion plasma over extended periods. The necessity of high-power gyrotrons for Electron Cyclotron Resonance Heating (ECRH) in controlled fusion has been thoroughly demonstrated through their development and rigorous testing. An essential realization is that the energy output of a fusion reactor is directly proportional to the number of fusion reactions occurring within its core. Consequently, the fusion community places significant emphasis on achieving larger core sizes, a focal point to enhance energy generation and reduce electricity production costs in future fusion tokamak. As the journey towards commercial fusion power continues, gyrotrons face novel challenges. Future tokamak designs demand gyrotrons capable of operating at higher frequencies and power levels to meet evolving challenges. Additionally, ensuring the reliability and enhanced tritium self-sufficiency of gyrotrons is imperative—a critical aspect for the operation of the futuristic fusion tokamak. The recent development of the DEMOnstration (DEMO) tokamak, representing the first prototype of a commercial Mon, 01 Jan 2024 00:00:00 GMT http://localhost:8081/jspui/handle/123456789/20403 2024-01-01T00:00:00Z http://localhost:8081/jspui/handle/123456789/20385 Title: THROUGHPUT ENHANCEMENT USING RESOURCE ALLOCATION AND MASSIVE MIMO TECHNOLOGY IN CELLULAR SYSTEM Authors: Gupta, Priya Abstract: In thecomingyears,itisanticipatedthattheproliferationofsmartphones,tablets,smart terminals, andemergingapplications,includingmachine-typecommunications,willcause an explosionincellularnetworkdatatraffic.Consequently,futureradioaccessnetworks shall beabletoaccommodatevastconnectivity,diverseusersets,andtheuniquerequire- ments ofapplications.However,inadequateresources,suchasbandwidthandbasestation powerwhicharegenerallylimitedinnature,poseasignificantobstacle.Theunavailability of asufficientnumberofchannelshindersuseraccommodationwithinthecellandincreases powerconsumption.Moreover,massiveconnectivityamonguserscausesnetworkconges- tion withinthecellandleadstocoverageissueswhichaffectthequalityofcommunication and userexperience. In viewofthis,inthisthesis,wefirstdiscusstheresourceallocationissueandproposea channel assignmenttechniquewithauserfairness-basedpowerallocationstrategyforNon- Orthogonal MultipleAccess(NOMA)cellularnetworks.Ourgoalistomaximizethesystem throughput whileensuringthateveryusermaintainsaminimumdataratetosatisfyqualityof service requirementsandsuccessiveinterferencecancellationconstraints.Tosolvethisopti- mization issue,weemploytheexhaustivesearchmethodandCVX2.0MOSEKsolver-based approach forchannelallocationfollowedbypowerallocationacrossassignedchannels.We use thedifferencebetweentwoconvexfunctionsprogrammingtechniqueformodifyingthe nonconvexoptimizationproblemintoaconvexsub-problem;efficientandfairpoweralloca- tion acrosschannelsisachievedbysolvingthisconvexsub-problemiteratively. Wenextdiscusstheusers’coverageissueandconsidermulti-pairtwo-wayhalf-duplex massivemultiple-inputmultiple-output(mMIMO)relayingsystemwithmultipleuserpairs. Most oftheexistingmMIMOrelayinginvestigatespatiallycorrelatedRayleighfadingand only fewworkshaveconsidereduncorrelatedRicianfadingchannels.Theyalsoignorethe impact ofphaseshiftsintheline-of-sightcomponentduetochangesinuserlocationand hardwareeffects.We,therefore,consideramulti-pairmMIMOamplify-and-forwardre- lay systemwithspatiallycorrelatedRicianchannelalongwithphaseshifts.Wederivethe asymptotic closed-formexpressionsforSpectralEfficiency(SE)atthreedifferentpower scaling schemesbyusingacombinationofmaximal-ratio-combiningandmaximal-ratio- transmission (MRC/MRT)techniquesattherelay.Weassumethatthechannelisnotknown at therelay.Accordingly,phase-awareminimummeansquareerrorandphase-unawarelin- ear minimummeansquareerror-basedestimatorsareusedforchannelestimation. Wenextextendourabovehalf-duplexworktothefull-duplexrelayingsystemoverthe same channelscenarioandderivetheasymptoticclosed-formSEexpressionsatdifferent powerscalingschemesusingzero-forcingreceivers.ThenumericalvaluesoftheSEob- tained fromthederivedexpressionshowtheimpactofvaryingpilotpowerandloopinterfer- ence duetofull-duplexprotocol. After analyzingtheasymptoticSEperformances,wefinallyderivetheclosed-formex- pression forSignal-to-Interference-Noise-Ratio(SINR)usingMRC/MRTtechnique.The expression,soderived,isvalidforanyarbitrarynumberofantennas.Toperformavalidity check, wesimulatetheclosed-formandergodicSEexpressionsandshowthevalidityofthe lowerboundSINR(i.e.,closed-formSINR).Moreover,wealsoshedlightontheimpactof loop interferenceinfull-duplexsystems. Thus, themaincontributionofthethesisistheenhancementofspectralefficiencyand energyefficiencythroughappropriateandoptimalresourceallocationwhileprovidingim- provedusercoverage.Wefocusonoptimizingchannelandpowerdistributionindownlink NOMA systems.Inordertoextendcoveragetousers,weproposeamulti-pairamplify-and- forwardrelayschemeusingasharedhalf-duplexmMIMOrelay.Thisisfurtherextendedto a full-duplexsystemunderthesamechannelscenario. Thu, 01 Feb 2024 00:00:00 GMT http://localhost:8081/jspui/handle/123456789/20385 2024-02-01T00:00:00Z http://localhost:8081/jspui/handle/123456789/20337 Title: NEGATIVE CAPACITANCE EFFECTS IN MULTIDOMAIN FERROELECTRIC DEVICES FOR LOW VOLTAGE APPLICATIONS Authors: Singh, Khoirom Johnson Abstract: In recent decades, the burgeoning growth of mobile electronics has fueled the demand for high-speed and ultralow-power integrated circuits (ICs). Addressing this shift in computational technology requires creative solutions at both the material and device levels. Despite various strategies proposed over the last two decades to mitigate energy consumption in ICs, finding an effective and innovative solution remains challenging due to the intrinsic physical constraints of conventional complementary metal-oxide-semiconductor (CMOS) technology. Traditionally, the primary approach to reducing energy consumption in ICs has involved lowering the supply voltage. However, for CMOS field-effect transistors (CMOS FETs), this reduction comes with the trade-off of speed reduction or increased off-state leakage, attributed to the fundamental limitation of the subthreshold swing (SS) to 60 mV/decade, known as “Boltzmann’s Tyranny”. Motivated by this imperative need to curtail energy consumption in dense ICs, this thesis explores the concept of harnessing the negative capacitance (NC) effects in ferroelectric devices. The overarching motivation is to lower the supply voltage below one volt without compromising transistor performance, thereby addressing the challenge of “Boltzmann’s Tyranny” inherent in conventional CMOS FETs. Ferroelectric materials have become increasingly attractive as next-generation (beyond-CMOS) electronic device candidates because of their multidomain polarization switching characteristics. However, recent studies have predominantly focused on single-domain ferroelectricity and perovskite materials like lead zirconate titanate (PZT), which are not compatible with current CMOS technology. In this work, we present an extensive study on the NC effect in both CMOS compatible organic and inorganic ferroelectric materials, such as poly(vinylidene fluoride-co-trifluoroethylene) [P(VDF-TrFE)] and hafnium zirconium oxide [Hf0.5Zr0.5O2 (HZO)], utilizing the multidomain Ginzburg-Landau-Khalatnikov theory. Our investigation includes original ultrascaled ferroelectric gate stack designs, aiming to achieve sub-60 mV/decade operation for reducing energy consumption in ICs. Additionally, we explore various ferroelectric-based proof-of-concept devices such as Landau FET/NCFET designed for diverse applications, including passive and active voltage amplifiers, steep-slope logic devices and circuits, and mixed-signal circuit design. To facilitate this exploration, we develop several self-consistent device simulation frameworks and compact models rigorously calibrated with experimental data. The key findings of this thesis can be categorized into two main parts. Initially, we focus on introducing a robust technology computer-aided design (TCAD) modeling framework for realistic simulations of NC effects in devices utilizing organic ferroelectric materials. We also discuss calibration methodologies against experimental data, conduct sensitivity analyses on anisotropy constants, and explore non-quasistatic behaviors. The maximum switching speed of organic ferroelectric materials is predicted, and the performance of metal/organic ferroelectric/metal devices is compared with oxide ferroelectric-based devices. Following this, we concentrate on directly capturing the NC effect at an ultralow voltage with little energy dissipation in a multidomain P(VDF-TrFE) gate stack, comprehending its underlying physical mechanisms and dynamics. Additionally, we introduced a passive voltage amplifier and a stable hysteresis-free multidomain P(VDF-TrFE)-gated Landau FET/NCFET device. Simulation results demonstrate the feasibility of achieving hysteresis-free, sub-60 mV/decade operation of the Landau FET/NCFET with a minimum SS of 26.59 mV/decade. The benefits of this device are tested on digital logic circuit design, paving the way for high-speed and energy-efficient digital IC designs. In the latter part, our focus shifts to NC gate stacks using HZO ferroelectric material, outperforming alternatives like P(VDF-TrFE) and PZT with its direct CMOS compatibility and sub-10 nm scalability. We investigate the impact of HZO thickness, domain number, and process variations on HZO-device circuit co-design. This investigation provides crucial insights for optimizing designs and understanding the implications of these variations on Landau FET-based voltage amplifiers, inverters, and ring oscillators. The exploration concludes with an in-depth examination of the physical origin of the NC effect in HZO ferroelectric gate stacks. The bipolar-to-unipolar pulsing technique is employed to verify the NC effect. Predictions regarding the intrinsic switching speeds of HZO are presented, considering various polarization damping factors. The study delves into the underlying factors leading to negative drain-induced barrier lowering effects, negative differential resistance effects, and voltage amplifications observed in NCFETs. For GHz applications of the Landau FETs/NCFETs as low-power devices, the polarization damping factor should be 0.18 Ωcm to 0.22 Ωcm, or even a lesser value is desirable. This can be achieved through the reengineering of the ultrascaled ferroelectric material. A circuit-compatible hybrid compact model for leakage-aware NCFETs is developed, supporting both Landau and Preisach ferroelectric models, demonstrating the superior performance of NCFETs compared to conventional CMOS technology. The model is evaluated for various digital and mixed-signal circuit designs, such as an amplifier, inverter, 2:1 fork circuit, and ring oscillator in the Cadence Spectre environment. Our research underscores the potential of this device as a promising concept, demonstrating its ability to achieve high on-state current levels comparable to advanced CMOS technology but with a reduced supply voltage budget required for operating ICs in the more-Moore era. The ultimate goal of designing various ferroelectric gate stacks and Landau FETs/NCFETs is to expand technologies at more relaxed dimensions like bulk planar 32 nm and 45 nm nodes by improving performance and reducing power without scaling and at a lower cost than aggressive nodes. Overall, this thesis confirms that the Landau FETs/NCFETs can be used to advance NC electronics, potentially paving the way for beyond-CMOS technology. Mon, 01 Apr 2024 00:00:00 GMT http://localhost:8081/jspui/handle/123456789/20337 2024-04-01T00:00:00Z http://localhost:8081/jspui/handle/123456789/20312 Title: MODELING AND ANALYSIS OF SELF-HEATING EFFECT IN ADVANCED MULTI-GATE MOSFETS Authors: Kumar, Vivek Abstract: In the era of miniaturization, the scaling of nanoscale devices has led to a complete transformation of nanoscale device structures, such as the introduction of advanced multi-gate MOSFETs like FinFETs and Stacked Nanosheet Field Effect Transistors (SNFET). However, self-heating effect (SHE) becomes a concern because of their confined channels surrounded by low thermal conductive gate oxide and buried oxide layer in substrate. The thesis investigates SHE in advanced multi-gate MOSFETs and presents novel thermal circuit, device electro-thermal models and simulation paradigms further to analyze, and optimize their thermal characteristics and related reliabilities. To this end, in the first part of thesis a thermal circuit model is developed beyond the conventional SHE circuit model to represent realistic dynamic heating between electron and lattice in SOI-FinFET device. The model considered thermal non-equilibrium phenomena established at high electric fields or frequencies in nanoscale devices and accounted heat transfer to lattice through phonon mode coupling by physically justified circuit elements that capture both electron (hot carrier) and lattice (SHE) temperatures. The next chapter deals with systematic fin-pitch designing approach to mitigate SHE in multi-fin (MF) SOI-FinFET and a Cooperative Game Theory (CGT) framework was employed in this regard. Individual fin contribution to SHE was determined by a combination of T-CAD simulation and CGT model frameworks. Further, a fin pitch optimization rule has been developed, which was found to remain SHE bias and MF-FinFET contact geometry invariant. Since, SHE is nonhomogeneous in MF-FinFET because of variations in heat dissipative paths between fins to the ambience, deriving its analytical model is challenging. From T-CAD modeling of MF-FinFET we have found inter-fin thermal cross talk (TCT) due to non-uniform heat flow between the fins, which finally settles into steady state fin boundary temperatures. The results have been used to write boundary conditions for analytical modeling of SHE in MF-FinFET device, which is the scope of the next contributory chapter. Generalized SHE analytical model encompassing fin, source-drain (S/D) extension and spacer regions had been developed for a MF-FinFET having arbitrary fin numbers, which was later validated using calibrated MF-FinFET T-CAD data. Finally, a multiscale model is presented to predict SHE induced and deformation accelerated oxide breakdown (BD) in a 5 nm SNFET. Calibrated T-CAD setup was utilized to simulate SHE in SNFET while multi-physics simulation was used to determine process induced deformations in nanosheets and adjoining dielectric layers that comprise of hafnium oxide (HfO2) and silicon dioxide (SiO2) interfacial layer (IL). Further, change in defect formation energies (FE) were estimated due to same deformation effect in real space and non-uniform trap generation within dielectric layers wrapping the nanosheets was modelled using a standard thermochemical E model of trap generation with updated FE and SHE as model input. Further, a shortest path search algorithm (A*) was utilized to join the trap generation regions between nanosheets and gate contact depending on their local weights, such that critical BD path could be obtained as useful to assess gate dielectric reliability of SNFET. Concluding remarks and future directions of the thesis work are finally addressed. Fri, 01 Dec 2023 00:00:00 GMT http://localhost:8081/jspui/handle/123456789/20312 2023-12-01T00:00:00Z