http://localhost:8081/jspui/handle/123456789/29 2026-11-03T04:30:06Z 2026-11-03T04:30:06Z Kushwaha, Dinesh http://localhost:8081/jspui/handle/123456789/21763 2026-10-22T11:16:33Z 2024-09-01T00:00:00Z

Title: A CIRCUIT DESIGN FOR ROBUST SRAM COMPUTE-IN-MEMORY ARCHITECTURE Authors: Kushwaha, Dinesh Abstract: Artificial intelligence (AI) and machine learning (ML) are revolutionized technologies widely adopted to solve real-time problems such as speech recognition, facial recognition, cancer detection, and image classifications. Deep convolutional neural networks (CNNs) have succeeded exceptionally in AI/ML tasks. The CNN models have intensive multiplication and accumulation (MAC) computation and require ample memory space to store the pre-trained models. Therefore, they consume large amounts of power on traditional computing systems, restricting their implementations to resourceconstrained edge devices. The conventional computing system has limited memory bandwidth due to slow memory access time and consumes more power during the data movement between the processor and memory. This is known as the “Von-Neumann bottleneck.” Thus, there is a need to build domainspecific hardware primitives for energy-efficient and high-speed ML processing at the edge. Computein- memory (CiM) is an alternate hardware solution to overcome the limitations of traditional computing systems. The CiM enables the memory to perform the computations inside the memory array, where the data is locally stored. Therefore, CiM improves the energy-efficiency of the computing system by reducing the data movement between the computation unit and the memory array. The CiM also allows parallel computing, an inherent characteristic of the CNN. This thesis aims to explore the SRAM-based compute-in-memory architectures because SRAM technology is more mature and easily integrates with modern System On Chips (SoCs). First, in this thesis work, robust SRAM bit-cells have been developed and designed to support compute-in-memory 1-bit XNOR and accumulation (XAC) operation for binary neural networks (BNNs) and multi-bit MAC operation for CNNs. The proposed 10T1C SRAM bit-cell is robust and provides full-swing output in computation mode. The 10T1C XNOR SRAM bit-cell performs the inmemory 1-bit XAC operation without pre-charging the larger bitline capacitances and significantly reducing energy consumption per XAC operation. As a proof of concept and to show the application of the proposed 10T1C SRAM bit-cell, a small BNN has been implemented using 10T1C SRAM bitcell in compute-in-memory XNOR mode. The functional verification of BNN implementation was done through simulations using 65 nm CMOS technology. The proposed XNOR and accumulation (XAC) scheme is energy-efficient and achieves a high compute signal-to-noise ratio (CSNR). The achieved 1ns of latency and 2.36 fJ of energy consumption per XAC operation are (7.2×, 7.2×) and (2×, 1.31×) lower than state-of-the-art digital and analog compute in-memory (CIM) XAC schemes respectively. The proposed XAC design achieves an 8.6× improvement in figure-of-merit (FoM) over the prior stateof- the-art. Moreover, the (σ/μ) average of 0.2% from Monte Carlo simulations shows that the proposed XAC scheme is robust against systematic mismatch and process variations.

2024-09-01T00:00:00Z Singh, Shekhar Pratap http://localhost:8081/jspui/handle/123456789/21751 2026-09-24T07:17:26Z 2025-01-01T00:00:00Z

Title: DEVELOPMENT OF SIGNAL PROCESSING TECHNIQUES FOR SPATIAL MODULATION Authors: Singh, Shekhar Pratap Abstract: Spatial modulation (SM) is a transmission scheme that involves a larger set of radiating elements than the number of transmit/receive electronics. This facilitates high-rate MIMO implementation to have reduced signal processing and circuitry complexity, as well as an improved energy efficiency (EE). SM combined with Non-Orthogonal Multiple Access (SM-NOMA) is a technique that combines the advantages of NOMA’s power-domain multiplexing and SM’s antenna-based indexing to enhance SE and EE in wireless communication systems. SM-NOMA combines the spatial diversity provided by SM and the spectrum sharing capability of NOMA, resulting in a system with enhanced user capacity, reduced hardware complexity, and improved SE. NOMA has been combined with different variants of SM such as quadrature spatial modulation (QSM) and generalized spatial modulation (GSM), and are referred as QSM-NOMA and GSM-NOMA.

2025-01-01T00:00:00Z Mallika http://localhost:8081/jspui/handle/123456789/21750 2026-09-24T07:13:01Z 2025-06-01T00:00:00Z

Title: Vision-based Deep-learning Models for Gesture Synthesis and Recognition Authors: Mallika Abstract: Over the past few decades, the progress in gesture and sign language recognition systems has made human-computer interaction more intuitive and user-friendly. By enabling computers to understand and interpret human gestures and sign language, we have made significant strides toward making technology more accessible to a broader range of individuals. Moreover, gesture and sign language recognition systems have improved communication and accessibility for individuals with hearing or speech impairments. These systems can convert sign language into text or speech, enabling effective communication between individuals who use sign language and those who are not familiar with it. This breakthrough has expanded opportunities for social interaction, education, employment, and various aspects of daily life for people with hearing or speech impairments. Environmental factors and variations, such as self-occlusion, differences in hand size and shape, background noise, and changes in illumination, can greatly impact the accuracy and reliability of the recognition process. Self-occlusion occurs when parts of the hand or body obstruct each other, making it difficult to determine the boundaries of the gesture accurately. This can lead to errors in recognition and misinterpretation of the intended gesture. Some methods aim to minimize the impact of these noises and improve recognition accuracy. Despite the difficulties posed by environmental noises, ongoing research in gesture recognition continues to explore novel algorithms, machine learning models, and sensor technologies to improve the robustness and accuracy of the recognition process. In this thesis, we take these challenges into account for designing various hand gesture algorithms such as static and dynamic hand gesture recognition systems, multiview gesture generation systems, and gesture-to-gesture systems. Many multiview recognition systems are available in the literature that deals with the problem of occlusion, but it requires the same gesture from different views. Collecting multiview data is a challenging task, as it requires the use of multiple cameras positioned at various angles or repeated performance of the actions to capture sufficient variability. To overcome this difficulty, we focus on generating different views of the input gesture using conditional multiview gesture synthesis. Static gestures are generated using paired data, with the generation algorithm designed to prioritize the perceptual and structural quality of the generated images as a primary objective. The aim is to generate realistic and visually appealing gestures that closely resemble the intended gestures. Once the views are generated, they are given as input into the proposed gesture recognition system for classification. This system employs a multiview approach for gesture recognition, utilizing decision-level fusion for improved accuracy.

2025-06-01T00:00:00Z Seema http://localhost:8081/jspui/handle/123456789/20490 2026-04-24T06:31:10Z 2024-03-01T00:00:00Z

Title: Analysis of multibit spin devices, memory and neural network Authors: Seema Abstract: In recent decades, the semiconductor industry has undergone remarkable growth, catalyzing a transformative impact on daily life through the evolution of electronic devices such as mobile phones and computers. This surge in technological advancements has concurrently intensified the demand for higher storage density. The emergence of spintronics has boosted storage capabilities by utilizing the effect of Tunnel Magnetoresistance. Magnetic Tunnel Junctions (MTJs), fundamental storage element in spintronics devices, have garnered interest due to their endurance, non-volatility, scalability, and compatibility with CMOS technologies. Different methods have been employed to write information into MTJs such as field-induced magnetic switching, spin transfer torque (STT), spin orbit torque (SOT), and voltage controlled magnetic anisotropy (VCMA). Single MTJ stores one bit per cell, hence, significant efforts have been made by the researchers to achieve multiple bits per cells by stacking multiple MTJs utilizing hybrid switching techniques such as STT, SOT and VCMA and a storage capacity up to 3 bits per cell has been achieved till now. Stacking of multiple MTJs is challenging because it requires additional writing steps that leads to additional footprint area, power, and latency overhead. Therefore, there is need to explore more novel structures or devices to achieve high storage density that overcomes these overheads. Magnetic Domain Wall (DW) devices have emerged as promising alternatives, offering high storage density, low driving current requirements, and improved cascading compared to existing technologies. DW memory has evolved from field-induced to current driven motion, resulting in advancements such as decreased bit size, improved thermal stability, and enhanced DW speed. However, scalability of DW devices is constrained by pinning defects along the nanowire. Therefore, it is a difficult task to develop an artificial pinning potential for storing magnetic bits at specific positions precisely. Various geometrical and non-geometrical techniques have been demonstrated to control and achieve the pinning of DWs. With increasing efforts, there is a growing need to explore innovative approaches to create, propagate, and detect the magnetic DWs in order to propel advancements in research and development. Despite their potential, applying DW devices at the circuit and system level remains challenging due to the gap between device physics and hardware circuit design. Existing dynamic-based compact models do not include all the factors responsible for the motion of the DW, hence, there is a need for a more accurate and robust model that considers all factors influencing DW motion.

2024-03-01T00:00:00Z